Abstract: An extreme low-k (ELK) dielectric film scheme for advanced interconnects includes an upper ELK dielectric layer and a lower ELK dielectric with different refractive indexes. The refractive index of the upper ELK dielectric layer is greater than the refractive index of the lower ELK dielectric layer.

Abstract: An extreme low-k (ELK) dielectric film scheme for advanced interconnects includes an upper ELK dielectric layer and a lower ELK dielectric with different refractive indexes. The refractive index of the upper ELK dielectric layer is greater than the refractive index of the lower ELK dielectric layer.

Abstract: A semiconductor structure having improved adhesion between a low-k dielectric layer and the underlying layer and a method for forming the same are provided. The semiconductor substrate includes a dielectric layer over a semiconductor substrate, an adhesion layer on the dielectric layer wherein the adhesion layer comprises a transition sub-layer over an initial sub-layer, and wherein the transition sub-layer has a composition that gradually changes from a lower portion to an upper portion. A low-k dielectric layer is formed on the adhesion layer. Damascene openings are formed in the low-k dielectric layer. A top portion of the transition sub-layer has a composition substantially similar to a composition of the low-k dielectric layer. A bottom portion of the transition sub-layer has a composition substantially similar to a composition of the initial sub-layer.

Abstract: A method for forming a cap layer for an interconnect structure is provided. The method includes providing a substrate; depositing a low-k dielectric layer comprising a first porogen over the substrate; depositing a low-k cap layer comprising a second porogen on the low-k dielectric layer; and curing the low-k dielectric layer and the low-k cap layer simultaneously to remove the first and the second porogens, so that a first porosity in the low-k dielectric layer and a second porosity in the low-k cap layer are created. The second porosity is preferably less than the first porosity. Preferably, the low-k dielectric layer and the low-k cap layer comprise a common set of precursors and porogens, and are in-situ performed.

Abstract: An integrated circuit includes an etch stop layer over a substrate; a UV blocker layer on the etch stop layer, wherein the UV blocker layer has a high extinction coefficient; and a low-k dielectric layer on the UV blocker layer.

Abstract: A HDP CVD process for depositing a USG liner followed by a FSG dielectric layer on a metal line pattern is described. The substrate is heated in a chamber with a plasma comprised of Ar and O2. A USG liner is deposited in two steps wherein the first step is without an RF bias and the second step is with a moderate RF bias that does not damage the metal lines or an anti-reflective coating on the metal. The moderate RF bias is critical in forming a sputtering component that redeposits USG to form more uniform sidewalls and better coverage at top corners of metal lines. The USG deposition process has a good gap filling capability and significantly reduces device failure rate by preventing corrosion of metal lines during subsequent thermal process cycles. The method also includes a PECVD deposited FSG layer that is planarized to complete an IMD layer.

Abstract: A HDP CVD process for depositing a USG liner followed by a FSG dielectric layer on a metal line pattern is described. The substrate is heated in a chamber with a plasma comprised of Ar and O2. A USG liner is deposited in two steps wherein the first step is without an RF bias and the second step is with a moderate RF bias that does not damage the metal lines or an anti-reflective coating on the metal. The moderate RF bias is critical in forming a sputtering component that redeposits USG to form more uniform sidewalls and better coverage at top corners of metal lines. The USG deposition process has a good gap filling capability and significantly reduces device failure rate by preventing corrosion of metal lines during subsequent thermal process cycles. The method also includes a PECVD deposited FSG layer that is planarized to complete an IMD layer.