Patents by Inventor Fang Wu

Fang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12379536
    Abstract: An electronic device includes: a first substrate; a second substrate, disposed below the first substrate; a first protection element, disposed on a surface of the first substrate away from the second substrate; and a second protection element, disposed on a surface of the second substrate away from the first substrate, wherein a width of the insulating layer is different from a width of the second protection element.
    Type: Grant
    Filed: January 3, 2024
    Date of Patent: August 5, 2025
    Assignee: INNOLUX CORPORATION
    Inventors: Chi-Fang Wu, Chin-Lung Ting, I-Chang Liang
  • Publication number: 20250227877
    Abstract: This disclosure is directed to a water-cooling plate having a first heat exchanging plate, a second heat exchanging plate and a main body. The first heat exchanging plate has a first fin structure. The second heat exchanging plate has a second fin structure. The main body has a partition plate, a first communication port and a second communication port, the main body has a first recess and a second recess, disposed at two sides of the partition plate. The partition plate has a communication opening communicated to the first recess and the second recess. The first fin structure is accommodated in the first recess to define a first channel, and the second fin structure is accommodated in the second recess to define a second channel. The first communication port, the first channel, the communication opening, the second channel, the second communication port are connected with each other sequentially.
    Type: Application
    Filed: October 11, 2024
    Publication date: July 10, 2025
    Inventors: Kuan-Cheng LU, Chih-Hao HSIA, Yu-Wei CHEN, Wei-Fang WU, Meng-Yu CHEN
  • Patent number: 12354758
    Abstract: Provided in the present disclosure is a control system for a heat supply apparatus of a nuclear power plant, comprising: a first-stage pressure measurement means configured for measuring a first-stage pressure of a turbine to obtain a first-stage pressure signal; a high-exhaust pressure measurement means configured for measuring an exhaust pressure of a turbine high-pressure cylinder to obtain an exhaust pressure signal; a steam extraction heating flow rate measurement means configured for measuring a steam extraction heating flow rate to obtain a steam extraction heating flow rate signal; a data acquisition module configured for acquiring and transmitting the measured first-stage pressure signal, the measured exhaust pressure signal and the measured steam extraction heating flow rate signal to a core operation processing module; the core operation processing module; and a the signal output module.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: July 8, 2025
    Assignees: SHANDONG NUCLEAR POWER COMPANY LTD., STATE NUCLEAR ELECTRIC POWER PLANNING DESIGN & RESEARCH INSTITUTE CO., LTD
    Inventors: Fang Wu, Fei Liu, Guobin Xu, Bingzhuo Zhang, Jianwei Li, Zhibin Zhu, Xiangyu Wang, Xiangyang Cai, Yongfeng Zhou, Da Song, Zhaokai Xing, Hongjun Xie, Shanshan Wang, Jinfeng Yang, Xiang Huang
  • Patent number: 12355008
    Abstract: A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die.
    Type: Grant
    Filed: May 13, 2024
    Date of Patent: July 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu
  • Publication number: 20250183102
    Abstract: Provided are a multiple-level interconnect structure having a scatterometry test layer and a manufacturing method thereof. The multiple level interconnect structure includes a patterned reflective layer, a bulk reflective layer and a patterned test layer. The patterned reflective layer is disposed on a substrate and includes a first reflective pattern and a second reflective pattern separated from each other. The bulk reflective layer is disposed on the patterned reflective layer. The patterned test layer is disposed on the bulk reflective layer.
    Type: Application
    Filed: February 12, 2025
    Publication date: June 5, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Jia Fang Wu, Hsiang-Chieh Yen, Hsu-Sheng Huang, Zhi Jian Wang
  • Publication number: 20250184005
    Abstract: An optical transceiver module (10) includes a light transmitting-side circuit (102), a light receiving-side circuit (104), and a microcontroller (106). The microcontroller (106) transmits a light transmitting-side start-up signal (S1) to the light transmitting-side circuit (102) to start the light transmitting-side circuit (102), and after the microcontroller (106) transmits the light transmitting-side start-up signal (S1) to the light transmitting-side circuit (102), the microcontroller (106) transmits a light receiving-side start-up signal (S3) to the light receiving-side circuit (104) after a first delay duration to start the light receiving-side circuit (104).
    Type: Application
    Filed: January 23, 2024
    Publication date: June 5, 2025
    Inventors: Chi-Hsien SUN, Chieh-Ming CHENG, Pei-Fang WU
  • Patent number: 12312406
    Abstract: An anti-B7-H3 antibody, a preparation method therefor, a conjugate and an application thereof. The anti-B7-H3 antibody comprises a complementarity determining region: one or more of heavy chain CDR1, heavy chain CDR2, and heavy chain CDR3, and/or one or more of light chain CDR1, light chain CDR2, and light chain CDR3. A sequence of the complementarity determining region is as described in the specification. The anti-B7-H3 antibody is a fully human antibody, has a unique antigen binding epitope, and can specifically bind B7-H3 antigen on tumor cells. Moreover, the antibody can rapidly internalize into cells after binding to tumor cells, and can be used for ADC drug development to obtain better anti-tumor activity and efficacy to achieve the purpose of treating cancers.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 27, 2025
    Assignee: SHANGHAI FUDAN-ZHANGJIANG BIO-PHARMACEUTICAL CO., LTD.
    Inventors: Qingsong Guo, Fang Wu, Tong Yang, Yijun Shen
  • Publication number: 20250166895
    Abstract: A system and method for providing and programming a programmable inductor is provided. The structure of the programmable inductor includes multiple turns, with programmable interconnects incorporated at various points around the turns to provide a desired isolation of the turns during programming. In an embodiment the programming may be controlled using the size of the vias, the number of vias, or the shapes of the interconnects.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Nien-Fang Wu
  • Patent number: 12288752
    Abstract: A semiconductor package includes a first die and a through via. The through via is electrically connected to the first die. The through via includes a first conductive layer having a first width, a second conductive layer having a second width different from the first width and a first seed layer disposed aside an interface between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Nien-Fang Wu, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Publication number: 20250114467
    Abstract: Disclosed are an anti-DLL3 antibody and a preparation method therefor, a drug conjugate and application thereof. The anti-DLL3 antibody in the present invention has good internalization activity, has better binding activity with human DLL3 protein, and has strong affinity at the protein level. The antibody conjugated drug targeting DLL3 in the present invention has good druggability, biological activity, and anti-tumor activity in vitro and vivo, and can achieve an application of cytotoxic drugs in treating tumor patients comprising SCLC and having neuroendocrine characteristics.
    Type: Application
    Filed: July 29, 2022
    Publication date: April 10, 2025
    Inventors: Qingsong GUO, Yijun SHEN, Tong YANG, Bei GAO, Fang WU, Likai MENG, Baoxia WANG, Wenbo ZHANG
  • Publication number: 20250111958
    Abstract: Provided in the present disclosure is a control system for a heat supply apparatus of a nuclear power plant, comprising: a first-stage pressure measurement means configured for measuring a first-stage pressure of a turbine to obtain a first-stage pressure signal; a high-exhaust pressure measurement means configured for measuring an exhaust pressure of a turbine high-pressure cylinder to obtain an exhaust pressure signal; a steam extraction heating flow rate measurement means configured for measuring a steam extraction heating flow rate to obtain a steam extraction heating flow rate signal; a data acquisition module configured for acquiring and transmitting the measured first-stage pressure signal, the measured exhaust pressure signal and the measured steam extraction heating flow rate signal to a core operation processing module; the core operation processing module; and a the signal output module.
    Type: Application
    Filed: February 15, 2023
    Publication date: April 3, 2025
    Applicants: SHANDONG NUCLEAR POWER COMPANY LTD., STATE NUCLEAR ELECTRIC POWER PLANNING DESIGN & RESEARCH INSTITUTE CO., LTD
    Inventors: Fang WU, Fei LIU, Guobin XU, Bingzhuo ZHANG, Jianwei LI, Zhibin ZHU, Xiangyu WANG, Xiangyang CAI, Yongfeng ZHOU, Da SONG, Zhaokai XING, Hongjun XIE, Shanshan WANG, Jinfeng YANG, Xiang HUANG
  • Patent number: 12255111
    Abstract: Provided are a multiple-level interconnect structure having a scatterometry test layer and a manufacturing method thereof. The multiple level interconnect structure includes a patterned reflective layer, a bulk reflective layer and a patterned test layer. The patterned reflective layer is disposed on a substrate and includes a first reflective pattern and a second reflective pattern separated from each other. The bulk reflective layer is disposed on the patterned reflective layer. The patterned test layer is disposed on the bulk reflective layer.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: March 18, 2025
    Assignee: United Microelectronics Corp.
    Inventors: Jia Fang Wu, Hsiang-Chieh Yen, Hsu-Sheng Huang, Zhi Jian Wang
  • Patent number: 12243681
    Abstract: A system and method for providing and programming a programmable inductor is provided. The structure of the programmable inductor includes multiple turns, with programmable interconnects incorporated at various points around the turns to provide a desired isolation of the turns during programming. In an embodiment the programming may be controlled using the size of the vias, the number of vias, or the shapes of the interconnects.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Nien-Fang Wu
  • Publication number: 20250057970
    Abstract: A TROP2 targeting antibody-drug conjugate, and a preparation method and use therefor. The antibody-drug conjugate is shown in formula I. Said type of compound has a good targeting property, a good inhibitory effect on tumor cells positively expressing TROP2, and good druggability and high safety. The present antibody drug conjugate has an inhibitory effect on TROP2, and also a good inhibitory effect on at least one of NCI-N87, MDA-MB-468 and BXPC3 cells.
    Type: Application
    Filed: September 13, 2024
    Publication date: February 20, 2025
    Inventors: Qingsong GUO, Yijun SHEN, Tong YANG, Bin BAO, Bei GAO, Fang WU, Jun XU
  • Publication number: 20250063693
    Abstract: A cooling device includes a tungsten alloy cooling pad (10), a first substrate (20), a second substrate (30) and multiple connecting columns (40). The tungsten alloy cooling pad (10) is used for being attached on the heat source (H). The first substrate (20) is parallelly superposed on the tungsten alloy cooling pad (10). The second substrate (30) corresponds to the first substrate (20) to be parallelly arranged. Each connecting column (40) is perpendicularly connected between the first substrate (20) and the second substrate (30). Each connecting column (40) is arranged in a matrix. Accordingly, the tungsten alloy cooling pad (10) can rapidly disperse and transfer the heat of the heat source (H) to the first substrate (20) and transfer to the second substrate (30) through each connecting column (40) for cooling to avoid heat accumulation leading to overheat.
    Type: Application
    Filed: January 5, 2024
    Publication date: February 20, 2025
    Inventors: Chi-Hsien SUN, Pei-Fang WU
  • Patent number: 12178880
    Abstract: An antibody-drug conjugate, and an intermediate thereof, a preparation method therefor, and an application thereof. Provided is an antibody-drug conjugate as represented by formula I. The compound has good targetability, has a good inhibitory effect on HER3-positive tumor cells, and has good druggability and high safety. The antibody-drug conjugate has an inhibitory effect on HER3, has an inhibitory effect on SK-BR-3 and SW620 cells, and also has a good inhibitory effect on at least one of 22Rv1, LNCaP, NCI-H820, OVCAR-8, and HCC827 cells.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: December 31, 2024
    Assignee: SHANGHAI FUDAN-ZHANGJIANG BIO-PHARMACEUTICAL CO., LTD.
    Inventors: Qingsong Guo, Yijun Shen, Tong Yang, Bin Bao, Bei Gao, Fang Wu, Jun Xu
  • Publication number: 20240427081
    Abstract: Optical devices and methods of manufacture are presented herein. In an embodiment, an optical device is provided that includes a first substrate, the first substrate including an optical device layer, and a semiconductor die, a first waveguide structure over the first substrate, the first waveguide structure including a first optical component surrounded by cladding material, wherein the first waveguide structure has a top surface, the top surface including a first portion at a first distance from the first substrate, a second portion at a second distance from the first substrate, and a transition portion between the first portion to the second portion, wherein the second distance is greater than the first distance, and a first reflective structure over the first portion and the transition portion, wherein a portion of the first reflective structure over the transition portion is a curved surface.
    Type: Application
    Filed: January 2, 2024
    Publication date: December 26, 2024
    Inventors: Chia-Ning Weng, Yu-Ming Chou, Shih Wei Liang, Nien-Fang Wu, Jiun Yi Wu, Chen-Hua Yu
  • Publication number: 20240411093
    Abstract: An optical component is provided. The optical component includes a silicon-based body including a bottom wall, a first side wall, a second side wall, and a micro lens structure. The first side wall is located on a first side of the silicon-based body and perpendicular to the bottom wall. The second side wall is located on a second side of the silicon-based body opposite to the first side, and forms an acute angle with the bottom wall. The micro lens structure is formed on the first side wall. The optical component further includes a protection layer formed over the first side wall and the micro lens structure.
    Type: Application
    Filed: June 12, 2023
    Publication date: December 12, 2024
    Inventors: Shih-Wei LIANG, Chen-Hua YU, Jiun-Yi WU, Nien-Fang WU
  • Publication number: 20240398970
    Abstract: A B7-H3 targeting antibody-drug conjugate, and a preparation method therefor and use thereof. Provided is the antibody-drug conjugate as shown in formula I. The compound has a good targeting property, good inhibitory effect on tumor cells positively expressing B7-H3, and good druggability and safety. The present antibody-drug conjugate has an inhibitory effect against B7-H3, and also a good inhibitory effect against at least one of NCI-N87, A375, LN-229, PA-1, MDA-MB-468, Calu-6 and HS-700T cells.
    Type: Application
    Filed: August 7, 2024
    Publication date: December 5, 2024
    Inventors: Qingsong GUO, Yijun SHEN, Tong YANG, Bin BAO, Bei GAO, Fang WU, Jun XU
  • Publication number: 20240387440
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a redistribution layer, a semiconductor die, conducting connectors, dummy bumps and an underfill. The semiconductor die is disposed on a top surface of the redistribution layer and electrically connected with the redistribution layer. The conducting connectors are disposed between the semiconductor die and the redistribution layer, and are physically and electrically connected with the semiconductor die and the redistribution layer. The dummy bumps are disposed on the top surface of the redistribution layer, beside the conducting connectors and under the semiconductor die. The underfill is disposed between the semiconductor die and the redistribution layer and sandwiched between the dummy bumps and the semiconductor die. The dummy bumps are electrically floating. The dummy bumps are in contact with the underfill without contacting the semiconductor die.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yang Yu, Nien-Fang Wu, Hai-Ming Chen, Yu-Min Liang, Jiun-Yi Wu