Patents by Inventor Fang-Yu Liang

Fang-Yu Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220246521
    Abstract: A package component, a semiconductor package and a manufacturing method thereof are provided. The package component for electrically coupling a semiconductor die includes a functional circuit structure and a seal ring structure embedded in an insulating layer. The semiconductor die disposed on the package component is electrically coupled to the functional circuit structure. The seal ring structure is electrically isolated from the functional circuit structure, the seal ring structure includes a stack of alternating interconnect layers and via patterns, the via pattern at each level of the stack includes first features spaced apart from one another and arranged at neighboring corners of the insulating layer, and the first features are offset lengthwise relative to each other to overlap therewith, and the first features are spaced apart widthwise relative to each other.
    Type: Application
    Filed: April 11, 2022
    Publication date: August 4, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Yu Liang, Kai-Chiang Wu
  • Patent number: 11374303
    Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a redistribution layer and a plurality of antenna patterns. The semiconductor die has an active surface and a backside surface opposite to the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is located on the active surface of the semiconductor die and over the insulating encapsulant. The plurality of antenna patterns is located over the semiconductor die, wherein the plurality of antenna patterns comprises a plurality of trenches located on a surface of the plurality of antenna patterns.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Yu Liang, Chih-Chiang Tsao
  • Patent number: 11309242
    Abstract: A package component, a semiconductor package and a manufacturing method thereof are provided. The package component for electrically coupling a semiconductor die includes an insulating layer, a functional circuit structure embedded in the insulating layer within a functional circuit region, and a seal ring structure embedded in the insulating layer within the seal ring region surrounding the functional circuit region. The semiconductor die disposed on the package component is electrically coupled to the functional circuit structure. The seal ring structure is electrically isolated from the functional circuit structure. The seal ring structure includes a stack of alternating interconnect layers and via patterns, and the via pattern at each level of the stack includes first features spaced apart from one another and arranged at neighboring corners of the seal ring region.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Yu Liang, Kai-Chiang Wu
  • Patent number: 11233019
    Abstract: A method including followings is provided. An encapsulated device including a semiconductor die and an insulating encapsulation laterally encapsulating the semiconductor die is provided. An insulating layer is formed over a surface of the encapsulated device. A groove pattern is formed on the insulating layer. A conductive paste is filled in the groove pattern and the conductive paste filled in the groove pattern is cured.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Yu Liang, Ching-Feng Yang, Kai-Chiang Wu
  • Publication number: 20210407904
    Abstract: A package component, a semiconductor package and a manufacturing method thereof are provided. The package component for electrically coupling a semiconductor die includes an insulating layer, a functional circuit structure embedded in the insulating layer within a functional circuit region, and a seal ring structure embedded in the insulating layer within the seal ring region surrounding the functional circuit region. The semiconductor die disposed on the package component is electrically coupled to the functional circuit structure. The seal ring structure is electrically isolated from the functional circuit structure. The seal ring structure includes a stack of alternating interconnect layers and via patterns, and the via pattern at each level of the stack includes first features spaced apart from one another and arranged at neighboring corners of the seal ring region.
    Type: Application
    Filed: June 29, 2020
    Publication date: December 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fang-Yu Liang, Kai-Chiang Wu
  • Publication number: 20210375809
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die laterally covered by an insulating encapsulation, a first redistribution structure disposed on the semiconductor die and the insulating encapsulation, a second redistribution structure disposed opposite to the first redistribution structure, and a through insulating via (TIV) penetrating through the insulating encapsulation. The semiconductor die is electrically coupled to the first redistribution structure through the second redistribution structure and the TIV. The first redistribution structure includes a patterned conductive layer covered by a patterned dielectric layer, and under-ball metallurgy (UBM) pattern partially covered by the patterned dielectric layer.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fang-Yu Liang, Hsiu-Jen Lin, Kai-Chiang Wu, Chih-Chiang Tsao
  • Publication number: 20210375774
    Abstract: A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.
    Type: Application
    Filed: August 15, 2021
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Yu Liang, Kai-Chiang Wu
  • Patent number: 11094642
    Abstract: A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Yu Liang, Kai-Chiang Wu
  • Publication number: 20200313278
    Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a redistribution layer and a plurality of antenna patterns. The semiconductor die has an active surface and a backside surface opposite to the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is located on the active surface of the semiconductor die and over the insulating encapsulant. The plurality of antenna patterns is located over the semiconductor die, wherein the plurality of antenna patterns comprises a plurality of trenches located on a surface of the plurality of antenna patterns.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fang-Yu Liang, Chih-Chiang Tsao
  • Publication number: 20200303331
    Abstract: A method including followings is provided. An encapsulated device including a semiconductor die and an insulating encapsulation laterally encapsulating the semiconductor die is provided. An insulating layer is formed over a surface of the encapsulated device. A groove pattern is formed on the insulating layer. A conductive paste is filled in the groove pattern and the conductive paste filled in the groove pattern is cured.
    Type: Application
    Filed: June 4, 2020
    Publication date: September 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fang-Yu Liang, Ching-Feng Yang, Kai-Chiang Wu
  • Publication number: 20200243454
    Abstract: A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.
    Type: Application
    Filed: April 15, 2020
    Publication date: July 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fang-Yu Liang, Kai-Chiang Wu
  • Patent number: 10720399
    Abstract: A semiconductor package includes an encapsulated semiconductor device, a first redistribution structure, an insulating layer, and an antenna. The encapsulated semiconductor device includes a semiconductor device encapsulated by an encapsulation material. The redistribution structure is disposed on a first side the encapsulated semiconductor device and electrically connected to the semiconductor device. The insulating layer is disposed on a second side of the encapsulated semiconductor device and comprises a groove pattern. The antenna is filled the groove pattern, wherein an upper surface of the antenna is substantially coplanar with an upper surface of the insulating layer.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fang-Yu Liang, Ching-Feng Yang, Kai-Chiang Wu
  • Publication number: 20200135669
    Abstract: A semiconductor package includes an encapsulated semiconductor device, a first redistribution structure, an insulating layer, and an antenna. The encapsulated semiconductor device includes a semiconductor device encapsulated by an encapsulation material. The redistribution structure is disposed on a first side the encapsulated semiconductor device and electrically connected to the semiconductor device. The insulating layer is disposed on a second side of the encapsulated semiconductor device and comprises a groove pattern. The antenna is filled the groove pattern, wherein an upper surface of the antenna is substantially coplanar with an upper surface of the insulating layer.
    Type: Application
    Filed: October 25, 2018
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fang-Yu Liang, Ching-Feng Yang, Kai-Chiang Wu
  • Patent number: 10629539
    Abstract: A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fang-Yu Liang, Kai-Chiang Wu
  • Publication number: 20190139897
    Abstract: A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.
    Type: Application
    Filed: December 14, 2017
    Publication date: May 9, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fang-Yu Liang, Kai-Chiang Wu
  • Patent number: 10199341
    Abstract: Provided is a substrate structure, including: a substrate body having a conductive contact; an insulating layer formed on the substrate body with the conductive contact exposed therefrom; and an insulating protection layer formed on a portion of a surface of the insulating layer, and having a plurality of openings corresponding to the conductive contact, wherein at least one of the openings is disposed at an outer periphery of the conductive contact. Accordingly, the insulating protection layer uses the openings to dissipate and disperse residual stresses in a manufacturing process of high operating temperatures.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: February 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Yu Liang, Hung-Hsien Chang, Yi-Che Lai, Wen-Tsung Tseng, Chen-Yu Huang
  • Patent number: 10062651
    Abstract: A packaging substrate is provided, which includes: a substrate body having a first region with a plurality of conductive pads and a second region adjacent to the first region, and a material layer formed on the second region to prevent the substrate body from warping. An electronic package having the packaging substrate is also provided.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: August 28, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Yu Liang, Hung-Hsien Chang, Yi-Che Lai, Chang-Fu Lin
  • Patent number: 10049975
    Abstract: A substrate structure is provided, including a substrate body having a conductive pad, an insulation layer formed on the substrate body and exposing the conductive pad, a conductive pillar disposed on the conductive pad, and a metal pad disposed on the insulation layer and electrically connected to the conductive pillar. A conductive component can be coupled to the metal pad. During a high-temperature process, the conductive pillar and the metal pad disperse the remaining stress generated due to heat, thereby preventing the conductive component from being cracked.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: August 14, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Yu Liang, Hung-Hsien Chang, Yi-Che Lai, Wen-Tsung Tseng, Chen-Yu Huang
  • Publication number: 20170317040
    Abstract: Provided is a substrate structure, including: a substrate body having a conductive contact; an insulating layer formed on the substrate body with the conductive contact exposed therefrom; and an insulating protection layer formed on a portion of a surface of the insulating layer, and having a plurality of openings corresponding to the conductive contact, wherein at least one of the openings is disposed at an outer periphery of the conductive contact. Accordingly, the insulating protection layer uses the openings to dissipate and disperse residual stresses in a manufacturing process of high operating temperatures.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 2, 2017
    Inventors: Fang-Yu Liang, Hung-Hsien Chang, Yi-Che Lai, Wen-Tsung Tseng, Chen-Yu Huang
  • Publication number: 20170229386
    Abstract: A substrate structure is provided, including a substrate body having a conductive pad, an insulation layer formed on the substrate body and exposing the conductive pad, a conductive pillar disposed on the conductive pad, and a metal pad disposed on the insulation layer and electrically connected to the conductive pillar. A conductive component can be coupled to the metal pad. During a high-temperature process, the conductive pillar and the metal pad disperse the remaining stress generated due to heat, thereby preventing the conductive component from being cracked.
    Type: Application
    Filed: September 7, 2016
    Publication date: August 10, 2017
    Inventors: Fang-Yu Liang, Hung-Hsien Chang, Yi-Che Lai, Wen-Tsung Tseng, Chen-Yu Huang