Abstract: A fast burst program sequence that reduces overall NAND flash programming time is disclosed. The burst program sequence includes maintaining a charge pump in an ON state and not fully discharging the WL/BLs at the conclusion of the programming phase of each program operation. As a result, the fast burst program sequence provides total program time savings over an existing cache program sequence by eliminating the full WL/BL discharge and charge pump reset that conventionally occurs after each program operation, which in turn, allows for the transfer of next page data from the page buffer to the data latches to be hidden within the program time of a prior/current program operation.

Abstract: A command/address sequence associated with a read/write operation for a memory device that utilizes an existing test data bus in a novel way that obviates the need to utilize an I/O bus for the command/address sequence. As such, the command/address sequence can be performed in parallel with the read/write operations, thereby removing a performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence detects a first enable signal and a data signal on the test data bus and decodes the data signal to obtain at least one of a command latch enable signal and address latch enable signal and at least one of a command code and an address code.

Abstract: A fast burst program sequence that reduces overall NAND flash programming time is disclosed. The burst program sequence includes maintaining a charge pump in an ON state and not fully discharging the WL/BLs at the conclusion of the programming phase of each program operation. As a result, the fast burst program sequence provides total program time savings over an existing cache program sequence by eliminating the full WL/BL discharge and charge pump reset that conventionally occurs after each program operation, which in turn, allows for the transfer of next page data from the page buffer to the data latches to be hidden within the program time of a prior/current program operation.

Abstract: Techniques disclosed herein cope with temperature effects in non-volatile memory systems. A control circuit is configured to sense a current temperature of the memory system and read, verify, program, and erase data in non-volatile memory cells by modifying one or more read/verify/program/erase parameters based on a temperature compensation value. The control circuit is further configured to read, verify, program, and erase data by accessing a historical temperature value stored in the memory system, the historical temperature value comprising a temperature at which a previous read, verify, program or erase occurred and measuring a current temperature value. The control circuit determines the temperature compensation value by applying a smoothing function.

Abstract: Countermeasure method for programming a non-defective plane of a non-volatile memory experiencing a neighbor plane disturb, comprising, once a first plane is determined to have completed programming of a current state but where not all planes have completed the programming, a loop count is incremented and a determination is made as to whether the loop count exceeds a threshold. If so, programming of the incomplete plane(s) is ceased and programming of the completed plane(s) is resumed by suspending the loop count and bit scan mode, and, on a next program pulse, applying a pre-determined rollback voltage to decrement a program voltage bias. The loop count and bit scan mode are resumed once a threshold voltage level equals a program voltage bias when the loop count was last incremented. BSPF criterion is applied for each programmed state. Advancement to the next loop only occurs if a programmed state is determined incomplete.

Abstract: A data storage system includes a storage medium including a plurality of strings of single-level cell (SLC) memory cells connected to a plurality of word lines; and a storage controller in communication with the storage medium, the storage controller including write circuitry configured to write data to the storage medium by: selecting a first word line of the plurality of word lines, the first word line being connected to a first plurality of strings; consecutively programming a first group of memory cells of the first plurality of strings connected to the first word line; and subsequent to programming the first group of memory cells, consecutively verifying respective programming results of the first group of memory cells.

Abstract: Techniques disclosed herein cope with temperature effects in non-volatile memory systems. A control circuit is configured to sense a current temperature of the memory system and read, verify, program, and erase data in non-volatile memory cells by modifying one or more read/verify/program/erase parameters based on a temperature compensation value. The control circuit is further configured to read, verify, program, and erase data by accessing a historical temperature value stored in the memory system, the historical temperature value comprising a temperature at which a previous read, verify, program or erase occurred and measuring a current temperature value. The control circuit determines the temperature compensation value by applying a smoothing function.

Abstract: Countermeasure method for programming a non-defective plane of a non-volatile memory experiencing a neighbor plane disturb, comprising, once a first plane is determined to have completed programming of a current state but where not all planes have completed the programming, a loop count is incremented and a determination is made as to whether the loop count exceeds a threshold. If so, programming of the incomplete plane(s) is ceased and programming of the completed plane(s) is resumed by suspending the loop count and bit scan mode, and, on a next program pulse, applying a pre-determined rollback voltage to decrement a program voltage bias. The loop count and bit scan mode are resumed once a threshold voltage level equals a program voltage bias when the loop count was last incremented. BSPF criterion is applied for each programmed state. Advancement to the next loop only occurs if a programmed state is determined incomplete.

Abstract: Apparatus and methods are described to program memory cells and control bit line discharge schemes during programming based on the data pattern. The memory controller can predict program data pattern based on SLC pulse number and TLC data completion signals and use these signals to adjust when the inhibited bit lines can discharge. Once a TLC program operation have more one data, the memory controller will enable EQVDDSA_PROG to equalize to VDDSA, and then discharge. In SLC program, the memory controller will enable EQVDDSA_PROG only in first program pulse and disable it thereafter.

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation. A control circuit is coupled to the word lines and the bit lines. The control circuit is configured to count a bit-scan quantity of the memory cells during a bit-scan of the program operation. The control circuit determines whether the bit-scan quantity of the plurality of memory cells is greater than at least one predetermined bit-scan threshold. In response to the bit-scan quantity of the memory cells being greater than the at least one predetermined bit-scan threshold, the control circuit is configured to adjust a word line ramp rate of a word line voltage applied to the word lines during the program operation.

Abstract: Apparatus and methods are described to program memory cells and control bit line discharge schemes during programming based on the data pattern. The memory controller can predict program data pattern based on SLC pulse number and TLC data completion signals and use these signals to adjust when the inhibited bit lines can discharge. Once a TLC program operation have more one data, the memory controller will enable EQVDDSA_PROG to equalize to VDDSA, and then discharge. In SLC program, the memory controller will enable EQVDDSA_PROG only in first program pulse and disable it thereafter.

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation. A control circuit is coupled to the word lines and the bit lines. The control circuit is configured to count a bit-scan quantity of the memory cells during a bit-scan of the program operation. The control circuit determines whether the bit-scan quantity of the plurality of memory cells is greater than at least one predetermined bit-scan threshold. In response to the bit-scan quantity of the memory cells being greater than the at least one predetermined bit-scan threshold, the control circuit is configured to adjust a word line ramp rate of a word line voltage applied to the word lines during the program operation.

Abstract: A data storage system includes a storage medium including a plurality of strings of single-level cell (SLC) memory cells connected to a plurality of word lines; and a storage controller in communication with the storage medium, the storage controller including write circuitry configured to write data to the storage medium by: selecting a first word line of the plurality of word lines, the first word line being connected to a first plurality of strings; consecutively programming a first group of memory cells of the first plurality of strings connected to the first word line; and subsequent to programming the first group of memory cells, consecutively verifying respective programming results of the first group of memory cells.

Abstract: Apparatuses and techniques are described for avoiding current consumption peaks during a program operation for a memory device. The timing of scan operations of latches is adjusted to avoid overlapping with an increase in word line voltages. The scan operations can include a pre-charge select scan, which identifies memory cells subject to a verify test, and a fill operation for latches of memory cells which fail a verify test in a prior program loop. The pre-charge select scan can occur before the increase in the word line voltages, while the fill operation occurs after the increase in word line voltages. In another approach, the start of the increase in the word line voltages is delayed when a state bit scan is expected to take a relatively long time, e.g., when a verify test is passed in a prior program loop.

Abstract: Apparatus and methods are described to program memory cells and verify stored values programmed into the cells. The next stage in stored memory can be moved to the current verification iteration when certain conditions are met. Verification can include counting bits that exceed a voltage value for a stage being verified to produce a bit count number and determining if the bit count number for the stage being verified meets a threshold value. If the bit count number does not meet the threshold, the verification process can continue with a current verify iteration and thereafter move to a next verify iteration. If the bit count number does meet the threshold, the process can add a next stage to the current verify iteration and thereafter move to a next verify iteration.

Abstract: Apparatus and methods are described to program memory cells and verify stored values programmed into the cells. The next stage in stored memory can be moved to the current verification iteration when certain conditions are met. Verification can include counting bits that exceed a voltage value for a stage being verified to produce a bit count number and determining if the bit count number for the stage being verified meets a threshold value. If the bit count number does not meet the threshold, the verification process can continue with a current verify iteration and thereafter move to a next verify iteration. If the bit count number does meet the threshold, the process can add a next stage to the current verify iteration and thereafter move to a next verify iteration.

Abstract: A trim component for a vehicle interior is disclosed. The trim component may provide an opening for airbag deployment and may comprise a substrate; a foam layer and a cover comprising a support layer coupled to a skin layer. The support layer may comprise at least one of polyurethane coating; two-component reactive aliphatic polyurethane; two-component reactive aromatic polyurethane; polyurea; acrylic elastomer; aromatic TPU; aliphatic TPU; TPO. The support layer may comprise a polyurethane coating. The polyurethane coating may be sprayed on the skin layer. The polyurethane coating may comprise a waterborne polyurethane. A thickness of the support layer may be generally less than a thickness of the skin layer. The trim component may comprise first and second features to facilitate deployment of the airbag through the opening. The support layer may limit fragmentation/separation of the skin layer during airbag deployment. The trim component may comprise an instrument panel.

Abstract: A trim component for a vehicle interior is disclosed. The trim component may provide an opening for airbag deployment and may comprise a substrate; a foam layer and a cover comprising a support layer coupled to a skin layer. The support layer may comprise at least one of polyurethane coating; two-component reactive aliphatic polyurethane; two-component reactive aromatic polyurethane; polyurea; acrylic elastomer; aromatic TPU; aliphatic TPU; TPO. The support layer may comprise a polyurethane coating. The polyurethane coating may be sprayed on the skin layer. The polyurethane coating may comprise a waterborne polyurethane. A thickness of the support layer may be generally less than a thickness of the skin layer. The trim component may comprise first and second features to facilitate deployment of the airbag through the opening. The support layer may limit fragmentation/separation of the skin layer during airbag deployment. The trim component may comprise an instrument panel.

Abstract: A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.

Abstract: A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.