Abstract: A circuit for outputting reference voltage includes: a detecting unit, a feedback unit and an output unit which are respectively connected with an external power source, wherein a plurality of field effect transistors (FETs) are provided in the detecting unit, wherein the detecting unit is for detecting foundry corners of the FETs therein, the feedback unit is for feeding back and comparing a detecting result of the detecting unit, and outputting information after feeding back and comparing, and the output unit is for outputting reference voltage corresponding to the foundry corners of the FETs to an external output terminal. The reference voltage outputted by the circuit for outputting reference voltage of the present invention is capable of varying with foundry corners of the FETs, and achieves compensating for foundry corners of the FETs.

Abstract: A differential signal detecting device includes a secondary amplifier; a front-end receiver and a final amplifier which are respectively connected to the secondary amplifier; and a signal outputter which is connected to the final amplifier. The front-end receiver receives two externally inputted channels of differential signals and an externally inputted reference threshold voltage, differentiates and transduces the two channels of differential signals. The secondary amplifier receives and amplifies the signals which are outputted by the front-end receiver, and outputs the signals amplified again. The final amplifier differentiates and amplifies the signals outputted by the secondary amplifier and outputs the two channels of differentiated signals. The signal outputter receives the two channels of differentiated signals which are outputted by the final amplifier and processes the two channels of differentiated signals with a logical conjunction before outputting.

Abstract: A frequency multiplier circuit includes a first signal input terminal, a second signal input terminal, an output terminal, a power source terminal, a ground terminal, a main control circuit which is connected to the first signal input terminal, the second signal input terminal, the power source terminal and the ground terminal, a reference circuit which is connected to the power source terminal and the ground terminal, and a frequency synthesis circuit which is connected to the main control circuit, the reference circuit, the output terminal, the power source terminal and the ground terminal.

Abstract: A driver having low power consumption includes a first input terminal, a second input terminal, an output terminal, a power supply terminal, a ground terminal, a driving circuit, an adjusting circuit connected to the driving circuit and a biasing circuit which is connected to the driving circuit and the adjusting circuit. A method for accomplishing low power consumption of a driver is also provided. The method accomplishes an object of low power consumption by dynamically adjusting a driving current of a driver according to a difference between inputted differential signals.

Abstract: A driver having low power consumption includes a first input terminal, a second input terminal, an output terminal, a power supply terminal, a ground terminal, a driving circuit, an adjusting circuit connected to the driving circuit and a biasing circuit which is connected to the driving circuit and the adjusting circuit. A method for accomplishing low power consumption of a driver is also provided. The method accomplishes an object of low power consumption by dynamically adjusting a driving current of a driver according to a difference between inputted differential signals.

Abstract: A PLL system includes: an input end; an output end; a first PFD; a first CHP connected to the first PFD; a first LPF connected to the first CHP; a first VCO connected to the first CHP and the first LPF; a second PFD connected to the first VCO; a second CHP connected to the second PFD; a second LPF connected to the second CHP; a second VCO connected to the second CHP and the second LPF; a first DIV connected to the first PFD and the second VCO; and a second DIV connected to the second PFD and the second VCO. A working method of the PLL system is also provided, which can restrain input noise as well as phase noise of the second VOC in such a manner that noise of the PLL system is well restrained.

Abstract: A circuit for outputting reference voltage includes: a detecting unit, a feedback unit and an output unit which are respectively connected with an external power source, wherein a plurality of field effect transistors (FETs) are provided in the detecting unit, wherein the detecting unit is for detecting foundry corners of the FETs therein, the feedback unit is for feeding back and comparing a detecting result of the detecting unit, and outputting information after feeding back and comparing, and the output unit is for outputting reference voltage corresponding to the foundry corners of the FETs to an external output terminal. The reference voltage outputted by the circuit for outputting reference voltage of the present invention is capable of varying with foundry corners of the FETs, and achieves compensating for foundry corners of the FETs.

Abstract: A frequency multiplier circuit with a function of automatically adjusting a duty cycle of an output signal includes an input terminal, a first detecting unit, a second detection unit, a duty cycle adjusting unit and a ground terminal; wherein the frequency multiplier control unit includes a first buffer, an AND gate, a first NOR gate and a second NOR gate; wherein the first detecting unit includes an inverter, a first resistance and a first capacitance; wherein the second detecting unit includes a second buffer, a second resistance and a second capacitance; wherein the duty cycle adjusting unit includes a comparator connected to the first resistance, the first capacitance, the second resistance, the second capacitance and the first buffer. The present invention also provides a frequency multiplier system thereof. The present invention is capable of automatically adjusting a duty cycle of an output signal to 50%.

Abstract: A differential signal detecting device includes a secondary amplifier; a front-end receiver and a final amplifier which are respectively connected to the secondary amplifier; and a signal outputter which is connected to the final amplifier. The front-end receiver receives two externally inputted channels of differential signals and an externally inputted reference threshold voltage, differentiates and transduces the two channels of differential signals. The secondary amplifier receives and amplifies the signals which are outputted by the front-end receiver, and outputs the signals amplified again. The final amplifier differentiates and amplifies the signals outputted by the secondary amplifier and outputs the two channels of differentiated signals. The signal outputter receives the two channels of differentiated signals which are outputted by the final amplifier and processes the two channels of differentiated signals with a logical conjunction before outputting.

Abstract: A resistance calibrating circuit includes an external power source; a reference unit, a current calibrating circuit and a voltage calibrating unit which are respectively connected to the external power source; an external reference voltage which is respectively connected to the reference unit and the voltage calibrating unit; an to-be-calibrated voltage-controlled resistor which is respectively connected to the current calibrating unit and the voltage calibrating unit, wherein the current calibrating unit is further connected to the reference unit. The resistance calibrating circuit is capable of automatically adjusting a resistance of the to-be-calibrated voltage-controlled resistor highly precisely and highly efficiently.

Abstract: A high speed signal detecting circuit includes an input terminal, a reference terminal, an output terminal, a power source terminal, a ground terminal, a front-end receiver which is connected to the input terminal, the reference terminal and the ground terminal, a secondary amplifier which is connected to the front-end receiver and the ground terminal, a final amplifier which is connected to the secondary receiver, the output terminal, the power source terminal and the ground terminal, and a biasing circuit which is connected to the front-end receiver, the secondary amplifier, the final amplifier, the power source terminal and the ground terminal. A high speed signal detecting method is also provided to precisely detect high speed signal and change a detection threshold value of the high speed signals by changing a voltage value of the reference terminal and thus has a great flexibility.

Abstract: A frequency multiplier circuit includes a first signal input terminal, a second signal input terminal, an output terminal, a power source terminal, a ground terminal, a main control circuit which is connected to the first signal input terminal, the second signal input terminal, the power source terminal and the ground terminal, a reference circuit which is connected to the power source terminal and the ground terminal, and a frequency synthesis circuit which is connected to the main control circuit, the reference circuit, the output terminal, the power source terminal and the ground terminal.

Abstract: A charge pump circuit includes a switching circuit for providing a charge and discharge current, and a control circuit for controlling the switching circuit. The switching circuit includes a first switch for controlling the charging speed. The control circuit generates a signal for controlling the first switch based on the pulse width of the input signal. The charge pump circuit of the present invention quickens the locking time of the phase locked loop.

Abstract: A frequency multiplier circuit with a function of automatically adjusting a duty cycle of an output signal includes an input terminal, a first detecting unit, a second detection unit, a duty cycle adjusting unit and a ground terminal; wherein the frequency multiplier control unit includes a first buffer, an AND gate, a first NOR gate and a second NOR gate; wherein the first detecting unit includes an inverter, a first resistance and a first capacitance; wherein the second detecting unit includes a second buffer, a second resistance and a second capacitance; wherein the duty cycle adjusting unit includes a comparator connected to the first resistance, the first capacitance, the second resistance, the second capacitance and the first buffer. The present invention also provides a frequency multiplier system thereof. The present invention is capable of automatically adjusting a duty cycle of an output signal to 50%.

Abstract: A transforming circuit between parallel data and serial data includes a current source, a clock input sub-circuit, and a parallel data input sub-circuit. The clock input sub-circuit includes a first clock signal terminal and a second clock signal terminal. The transforming circuit between parallel data and serial data also includes a clock control sub-circuit and a serial data output control sub-circuit. The clock control sub-circuit includes four switching elements. A first and a third switching elements are controlled by the second clock signal terminal, and a second and a fourth switching elements are controlled by the first clock signal terminal. The serial data output control sub-circuit includes a fifth switching element and a sixth switching element to speed up the falling edge of the output signal flip, a seventh switching element and an eighth switching element to limit the output signal amplitude. A transforming system thereof is also provided.

Abstract: A current source circuit with high order temperature compensation, includes a reference voltage terminal, a first power module, a second power module, a control module, a current source output module and a bias current source module. The control module includes a first field-effect tube (FET), a second FET, and a third FET. The bias current source module includes a first bias current source and a second bias current source. The current source output module includes a fourth FET, a fifth FET, and an output terminal. The first power module includes a first comparator, a sixth FET, a first resistor and a second resistor. The second power module includes a second comparator, a seventh FET, a third resistor, and a fourth resistor. A current source system with high order temperature compensation is further provided.

Abstract: An automatic bias operational amplifying circuit, includes a control sub-circuit and an offset sub-circuit connected to the control sub-circuit. The control sub-circuit includes a first input terminal, a second input terminal, a first field-effect transistor connected to the offset sub-circuit, a second field-effect transistor connected to the first input terminal, a third field-effect transistor connected to the second input terminal, a first output terminal connected to the second field-effect transistor, a second output terminal connected to the third field-effect transistor, a first resistor connected to the first output terminal, and a second resistor connected to the second output terminal.

Abstract: A common-mode feedback circuit includes an amplifying circuit, a biasing circuit connected with the amplifying circuit, and a feedback loop connecting the amplifying circuit with the biasing circuit. The feedback loop includes a first field effect transistor M1, a eighth field effect transistor M1B connected with the first field effect transistor M1, a tenth field effect transistor M2B and an eleventh field effect transistor MFB connecting the eighth field effect transistor M1B and the tenth field effect transistor M2B. The common-mode voltage value of the common-mode feedback circuit is adjusted by the eleventh field effect transistor MFB. The common-mode feedback circuit has the simple structure and is capable of achieving the common-mode feedback without the peripheral feedback circuit and the input reference voltage.

Abstract: A transforming circuit between parallel data and serial data includes a current source, a clock input sub-circuit, and a parallel data input sub-circuit. The clock input sub-circuit includes a first clock signal terminal and a second clock signal terminal. The transforming circuit between parallel data and serial data also includes a clock control sub-circuit and a serial data output control sub-circuit. The clock control sub-circuit includes four switching elements. A first and a third switching elements are controlled by the second clock signal terminal, and a second and a fourth switching elements are controlled by the first clock signal terminal. The serial data output control sub-circuit includes a fifth switching element and a sixth switching element to speed up the falling edge of the output signal flip, a seventh switching element and an eighth switching element to limit the output signal amplitude. A transforming system thereof is also provided.

Abstract: A charge pump circuit includes a switching circuit for providing a charge and discharge current, and a control circuit for controlling the switching circuit. The switching circuit includes a first switch for controlling the charging speed. The control circuit generates a signal for controlling the first switch based on the pulse width of the input signal. The charge pump circuit of the present invention quickens the locking time of the phase locked loop.