Abstract: A memory cell including a substrate having a first doped region and a second doped region spaced apart from each other and defining a channel region therebetween, a floating gate including a first end over the channel region and a second end over the first doped region, a control gate including a first portion arranged laterally adjacent to the second end of the floating gate and a second portion arranged over and overlapping the second end of the floating gate, a word line overlapping the channel region, the first end of the floating gate, and the second portion the control gate, a first insulation member separating the floating gate, the control gate and the word line from the substrate; a second insulation member separating the floating gate from the control gate, and a third insulation member separating the floating gate and the control gate from the word line.

Abstract: A memory cell including a substrate having a first doped region and a second doped region spaced apart from each other and defining a channel region therebetween, a floating gate including a first end over the channel region and a second end over the first doped region, a control gate including a first portion arranged laterally adjacent to the second end of the floating gate and a second portion arranged over and overlapping the second end of the floating gate, a word line overlapping the channel region, the first end of the floating gate, and the second portion the control gate, a first insulation member separating the floating gate, the control gate and the word line from the substrate; a second insulation member separating the floating gate from the control gate, and a third insulation member separating the floating gate and the control gate from the word line.

Abstract: Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memory cell region having a pair of non-volatile memory cells with a split gate. A split gate includes first and second gates. The first gate is an access gate and the second gate is a storage gate with a control gate over a floating gate. A common second S/D region is disposed adjacent to second gates of the first and second memory cells and first S/D regions are disposed adjacent to the first gates of the first and second memory cells. An erase gate is disposed over the common second S/D region. The erase gate is isolated by the second S/D and second gates by dielectric layers. A silicide block is disposed over the memory cell pair, covering the erase gate at least portions of the second gates of the memory cells.

Abstract: A method of forming a uniform WL over the MCEL region and resulting device are provided. Embodiments include providing a substrate having a MCEL region, a HV region and a logic region, separated by an isolation region; forming a plurality of CG stacks over the MCEL region, and a plurality of CG dummy stacks over the HV region and the logic region, respectively; forming first and second overlying polysilicon layers with a spacer therebetween, an EG and a WL on the MCEL region formed; planarizing the second polysilicon layer down to upper surface of the plurality of CG stacks and the plurality of CG dummy stacks; and removing portions of the second polysilicon layer in-between the plurality of CG stacks and around the plurality of CG dummy stacks.

Abstract: A method of forming a thick EG polysilicon over the FG and resulting device are provided. Embodiments include forming a CG on a substrate; forming an STI between a logic region and the CG; forming a polysilicon EG through the CG and CG HM; forming a polysilicon structure over the logic and STI; forming and overfilling with polysilicon a WL trench through the CG and CG HM, between the EG and STI; forming a buffer oxide in the polysilicon structure over the logic region and part of the STI; recessing the buffer oxide and etching back the polysilicon overfill down the CG HM; forming a second buffer oxide over the EG and logic region; recessing the WL polysilicon; removing the first and second buffer oxides; forming a mask with an opening over a center of the WL, the STI, and a majority of the logic region; and removing exposed polysilicon.

Abstract: Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memory cell region having a pair of non-volatile memory cells with a split gate. A split gate includes first and second gates. The first gate is an access gate and the second gate is a storage gate with a control gate over a floating gate. A common second S/D region is disposed adjacent to second gates of the first and second memory cells and first S/D regions are disposed adjacent to the first gates of the first and second memory cells. An erase gate is disposed over the common second S/D region. The erase gate is isolated by the second S/D and second gates by dielectric layers. A silicide block is disposed over the memory cell pair, covering the erase gate at least portions of the second gates of the memory cells.