Patents by Inventor Fangxing Wei
Fangxing Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11018676Abstract: Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.Type: GrantFiled: April 23, 2019Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Fangxing Wei, Khushal Chandan, Dan Shi, Michael Allen
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Patent number: 10797685Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.Type: GrantFiled: October 4, 2019Date of Patent: October 6, 2020Assignee: Micron Technology, Inc.Inventors: Dan Shi, Fangxing Wei, Michael J. Allen
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Publication number: 20200099370Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.Type: ApplicationFiled: October 4, 2019Publication date: March 26, 2020Inventors: Dan Shi, Fangxing Wei, Michael J. Allen
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Patent number: 10574241Abstract: Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for better tracking of environmental conditions. The phase compensation circuit can generate a linear code to apply phase compensation to lock phase of an I/O signal to a phase of a timing signal. The circuit selectively adjusts the linear code with a variable, programmable slope, where the slope defines how much phase compensation is applied per unit change in the linear code. The circuit applies the adjusted linear code to a lock loop to lock the phase of the I/O signal to the phase of the timing signal.Type: GrantFiled: February 16, 2017Date of Patent: February 25, 2020Assignee: Intel CorporationInventors: Fangxing Wei, Setul M. Shah, Michael J. Allen, Khushal N. Chandan
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Publication number: 20200007132Abstract: Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.Type: ApplicationFiled: April 23, 2019Publication date: January 2, 2020Applicant: Intel CorporationInventors: Fangxing Wei, Khushal Chandan, Dan Shi, Michael Allen
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Patent number: 10476488Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.Type: GrantFiled: November 8, 2018Date of Patent: November 12, 2019Assignee: Micron Technology, Inc.Inventors: Dan Shi, Fangxing Wei, Michael J. Allen
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Publication number: 20190207594Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.Type: ApplicationFiled: November 8, 2018Publication date: July 4, 2019Inventors: Dan Shi, Fangxing Wei, Michael J. Allen
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Patent number: 10270453Abstract: Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.Type: GrantFiled: April 2, 2016Date of Patent: April 23, 2019Assignee: Intel CorporationInventors: Fangxing Wei, Khushal Chandan, Dan Shi, Michael Allen
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Patent number: 10164618Abstract: Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.Type: GrantFiled: December 28, 2017Date of Patent: December 25, 2018Assignee: MICRON TECHNOLOGY, INC.Inventors: Dan Shi, Fangxing Wei, Michael J. Allen
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Patent number: 10122526Abstract: Technology for a phase detector is described. The phase detector can include a reference clock. The phase detector can include a feedback clock. The phase detector can include a first latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock. The phase detector can include a second latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state. The phase detector can include a third latch that loads the lead-lag status from the second latch when the reference clock and the feedback clock produce clock signals in a low state.Type: GrantFiled: April 1, 2017Date of Patent: November 6, 2018Assignee: Intel CorporationInventors: Fangxing Wei, Dan Shi, Michael J. Allen
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Publication number: 20180287774Abstract: Technology for a phase detector is described. The phase detector can include a reference clock. The phase detector can include a feedback clock. The phase detector can include a first latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock. The phase detector can include a second latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state. The phase detector can include a third latch that loads the lead-lag status from the second latch when the reference clock and the feedback clock produce clock signals in a low state.Type: ApplicationFiled: April 1, 2017Publication date: October 4, 2018Applicant: Intel CorporationInventors: Fangxing Wei, Dan Shi, Michael J. Allen
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Publication number: 20170337952Abstract: Examples may include techniques for dual-range clock duty cycle tuning of a clock signal used for an input/output data bus. A clock duty cycle of the clock signal is monitored to determine whether the clock duty cycle falls within a threshold of a 50 percent duty cycle. A dual-range tuning is then implemented until the clock duty cycle of the clock signal falls within the threshold.Type: ApplicationFiled: May 23, 2016Publication date: November 23, 2017Applicant: Intel CorporationInventors: Dan Shi, Fangxing Wei, Michael J. Allen
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Patent number: 9805773Abstract: Examples may include techniques for dual-range clock duty cycle tuning of a clock signal used for an input/output data bus. A clock duty cycle of the clock signal is monitored to determine whether the clock duty cycle falls within a threshold of a 50 percent duty cycle. A dual-range tuning is then implemented until the clock duty cycle of the clock signal falls within the threshold.Type: GrantFiled: May 23, 2016Date of Patent: October 31, 2017Assignee: Intel CorporationInventors: Dan Shi, Fangxing Wei, Michael J Allen
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Publication number: 20170288683Abstract: Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.Type: ApplicationFiled: April 2, 2016Publication date: October 5, 2017Applicant: Intel CorporationInventors: Fangxing Wei, Khushal Chandan, Dan Shi, Michael Allen
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Publication number: 20170237444Abstract: Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for better tracking of environmental conditions. The phase compensation circuit can generate a linear code to apply phase compensation to lock phase of an I/O signal to a phase of a timing signal. The circuit selectively adjusts the linear code with a variable, programmable slope, where the slope defines how much phase compensation is applied per unit change in the linear code. The circuit applies the adjusted linear code to a lock loop to lock the phase of the I/O signal to the phase of the timing signal.Type: ApplicationFiled: February 16, 2017Publication date: August 17, 2017Inventors: Fangxing Wei, Setul M. Shah, Michael J. ALLEN, Khushal N. Chandan
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Patent number: 9614533Abstract: Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for better tracking of environmental conditions. The phase compensation circuit can generate a linear code to apply phase compensation to lock phase of an I/O signal to a phase of a timing signal. The circuit selectively adjusts the linear code with a variable, programmable slope, where the slope defines how much phase compensation is applied per unit change in the linear code. The circuit applies the adjusted linear code to a lock loop to lock the phase of the I/O signal to the phase of the timing signal.Type: GrantFiled: June 19, 2015Date of Patent: April 4, 2017Assignee: Intel CorporationInventors: Fangxing Wei, Setul M Shah, Michael J Allen, Khushal N Chandan
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Patent number: 9548747Abstract: A glitch-free digitally controlled oscillator (DCO) code update may be achieved by synchronizing the transfer of the DCO code update to a logic state transition of a pulse in the DCO clock output signal such that the code update may be achieved while the DCO delay chain remains in the same logic state. A state machine may provide the DCO code update and a pulsed update signal to a timing circuit. The DCO code update may be aligned with a pulse in the pulsed update signal. The timing circuit may generate a DCO code update enabled signal upon alignment of the pulse in the pulsed update signal with a state transition of a pulse in the pulsed DCO clock output. The DCO code update enabled signal may be aligned with a state transition in the pulsed DCO clock output to permit a glitch-free DCO code update.Type: GrantFiled: May 15, 2015Date of Patent: January 17, 2017Assignee: INTEL CORPORATIONInventors: Fangxing Wei, Michael J. Allen, Setul M. Shah
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Publication number: 20160373119Abstract: Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for better tracking of environmental conditions. The phase compensation circuit can generate a linear code to apply phase compensation to lock phase of an I/O signal to a phase of a timing signal. The circuit selectively adjusts the linear code with a variable, programmable slope, where the slope defines how much phase compensation is applied per unit change in the linear code. The circuit applies the adjusted linear code to a lock loop to lock the phase of the I/O signal to the phase of the timing signal.Type: ApplicationFiled: June 19, 2015Publication date: December 22, 2016Inventors: Fangxing Wei, Setul M. Shah, Michael J. Allen, Khushal N. Chandan
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Publication number: 20160336943Abstract: A glitch-free digitally controlled oscillator (DCO) code update may be achieved by synchronizing the transfer of the DCO code update to a logic state transition of a pulse in the DCO clock output signal such that the code update may be achieved while the DCO delay chain remains in the same logic state. A state machine may provide the DCO code update and a pulsed update signal to a timing circuit. The DCO code update may be aligned with a pulse in the pulsed update signal. The timing circuit may generate a DCO code update enabled signal upon alignment of the pulse in the pulsed update signal with a state transition of a pulse in the pulsed DCO clock output. The DCO code update enabled signal may be aligned with a state transition in the pulsed DCO clock output to permit a glitch-free DCO code update.Type: ApplicationFiled: May 15, 2015Publication date: November 17, 2016Applicant: INTEL CORPORATIONInventors: FANGXING WEI, MICHAEL J. ALLEN, SETUL M. SHAH
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Patent number: 9455726Abstract: Phase compensation in an I/O (input/output) circuit includes a triangular control contour with a simplified generation circuit. A linear control circuit can generate a digital N-bit linear count, and route the least significant M bits [(M?1):0] for linear control for fine delay mixing of a phase compensation loop and the most significant (N?M) bits [(N?1):M] for linear control for coarse control of a delay chain for the phase compensation loop. Prior to decoding the least significant M bits for fine delay mixing, the control circuit performs a bitwise XOR (exclusive OR) of bit M with each of bits [(M?1):0] to generate M linear control bits as the linear control for fine delay mixing. The M linear control bits generate a linear control count having a triangular contour, where the linear control count continuously, repeatedly counts from 0 to (2M?1) to 0.Type: GrantFiled: June 19, 2015Date of Patent: September 27, 2016Assignee: Intel CorporationInventors: Fangxing Wei, Michael J Allen, Khushal N Chandan, Setul M Shah