Abstract: The present disclosure provides a server baseboard, relates to the field of computer technology and can be applied to the fields of cloud computing and big data. A specific implementation scheme is that the server baseboard includes: a main control program module, a switch chip connected to the main control program module, and a plurality of physical network ports for connecting the switch chip to a management network and a baseboard other than the baseboard where the main control program module is located. The server baseboard can reduce the construction cost of the management network, and improve the availability of a server and the security of a service network. The present disclosure also provides a server, a control method, an electronic apparatus, and a readable medium.

Abstract: This invention discloses a method for data transfer between a host memory and a flash memory module through direct memory access (DMA), and a related data-transfer subsystem. In one embodiment, the subsystem comprises a DMA controller, a flash-memory controller, a data buffer for buffering data transferred between the DMA controller and the flash-memory controller, and a status-register group for storing a current status of the data buffer. The DMA controller and the flash-memory controller are configured such that both of them are allowed to update the current status and to detect a change of the current status during the data transfer, so that a substantial part of the data transfer's process is executed through direct interaction between the DMA controller and the flash-memory controller without involving a central processing unit. The subsystem may further comprise a command storing unit for storing command packages for execution by the flash-memory controller.

Abstract: This invention discloses a method for data transfer between a host memory and a flash memory module through direct memory access (DMA), and a related data-transfer subsystem. In one embodiment, the subsystem comprises a DMA controller, a flash-memory controller, a data buffer for buffering data transferred between the DMA controller and the flash-memory controller, and a status-register group for storing a current status of the data buffer. The DMA controller and the flash-memory controller are configured such that both of them are allowed to update the current status and to detect a change of the current status during the data transfer, so that a substantial part of the data transfer's process is executed through direct interaction between the DMA controller and the flash-memory controller without involving a central processing unit. The subsystem may further comprise a command storing unit for storing command packages for execution by the flash-memory controller.