Patents by Inventor Fangyue Liu

Fangyue Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230395425
    Abstract: The embodiments herein relate to contact via structures of semiconductor devices and methods of forming the same. A semiconductor device is provided. The semiconductor device includes a substrate, a conductive feature, and a contact via structure. The conductive feature is over the substrate. The contact via structure is electrically coupled to the conductive feature and includes a curved concave profile throughout a height of the contact via structure and an upper width wider than the width of the conductive feature.
    Type: Application
    Filed: August 16, 2023
    Publication date: December 7, 2023
    Inventors: YUNG FU CHONG, RUI TZE TOH, FANGYUE LIU
  • Patent number: 11776844
    Abstract: The embodiments herein relate to contact via structures of semiconductor devices and methods of forming the same. A semiconductor device is provided. The semiconductor device includes a substrate, a conductive feature over the substrate, and a contact via structure over and electrically coupling to the conductive feature. The contact via structure has a concave profile.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: October 3, 2023
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yung Fu Chong, Rui Tze Toh, Fangyue Liu
  • Publication number: 20220310444
    Abstract: The embodiments herein relate to contact via structures of semiconductor devices and methods of forming the same. A semiconductor device is provided. The semiconductor device includes a substrate, a conductive feature over the substrate, and a contact via structure over and electrically coupling to the conductive feature. The contact via structure has a concave profile.
    Type: Application
    Filed: March 24, 2021
    Publication date: September 29, 2022
    Inventors: YUNG FU CHONG, RUI TZE TOH, FANGYUE LIU
  • Patent number: 9620418
    Abstract: Methods for fabricating integrated circuits having improved active regions are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a low voltage device area and in a high voltage device area. The method includes selectively forming voids between the isolation regions and the active regions in the high voltage device area to expose active side surfaces. The method further includes oxidizing the upper surface and the active side surfaces to form a gate oxide layer over the low voltage device area and the high voltage device area.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: April 11, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Liang Li, Wei Lu, Lian Choo Goh, Yung Fu Alfred Chong, Fangyue Liu, Alex See
  • Publication number: 20160133524
    Abstract: Methods for fabricating integrated circuits having improved active regions are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a low voltage device area and in a high voltage device area. The method includes selectively forming voids between the isolation regions and the active regions in the high voltage device area to expose active side surfaces. The method further includes oxidizing the upper surface and the active side surfaces to form a gate oxide layer over the low voltage device area and the high voltage device area.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 12, 2016
    Inventors: Liang Li, Wei Lu, Lian Choo Goh, Yung Fu Alfred Chong, Fangyue Liu, Alex See