Abstract: An example memory controller and readable storage medium are disclosed. An example memory system includes: a non-volatile memory device and a memory controller coupled to the non-volatile memory device; the memory controller is configured to: determine whether data for the logical block address mapping of a received read command belongs to tables of a first class or tables of a second class, and confirm the heat of the data corresponding to the logical block address of the received read command; determine a level of the amount of drift of a threshold voltage of a memory cell corresponding to the logical block address, according to the heat of the data corresponding to the logical block address of the received read command; determine different read voltages that are correspondingly sent to the memory cell corresponding to the logical block address, according to different levels of the amount of drift.

Abstract: Systems, devices, methods, and storage media for managing refreshment of memory cells in memory systems are provided. In one aspect, a memory system includes: a non-volatile memory device including a plurality of memory cells and a memory controller coupled to the non-volatile memory device. The memory controller is configured to: refresh adjacent memory cells of a target memory cell of the plurality of memory cells, when a count of write operations performed on the target memory cell within a preset time duration is greater than a preset threshold.

Abstract: In certain aspects, a memory system includes a non-volatile memory device and a memory controller coupled to the non-volatile memory device. The non-volatile memory device includes a plurality of memory groups. Each of the memory groups includes a plurality of memory units. The memory controller is configured to perform at least one of a first wear-leveling process by swapping a first memory group of the memory groups and a second memory group of the memory groups based on a first group write count for the first memory group and a second group write count for the second memory group, or a second wear-leveling process by swapping a first memory unit of the memory units and a second memory unit of the memory units based on a first unit write count for the first memory unit and a second unit write count for the second memory unit.

Abstract: The present disclosure involves methods, apparatuses, and computer-readable storage media for media scan in a memory system. In one example, a method for a memory system includes receiving commands from a host coupled to the memory system, wherein the memory system includes a memory device, the memory device includes a memory cell array, and the memory cell array includes a number of memory cells. The method further includes performing operations on the memory device based on the commands. The method further includes scanning at least a group of memory cells of the memory cell array by performing a number of scans within a scan period among the operations.

Abstract: A memory system includes a memory device including memory cells, and a memory controller coupled to the memory device. A memory cell is configured to be programmed to one of a first state and a second state. The first state corresponds to a first bit, and the second state corresponds to a second bit. The memory controller is configured to receive first data including bits, the bits of the first data including the first bit and the second bit, in response to a second number of the second bit in the first data being larger than a first number of the first bit in the first data, perform a first flipping operation to the first data to obtain a second data including the bits, and store the second data to the memory device.

Abstract: The present disclosure provides a memory system with a non-volatile memory that includes a plurality of storage areas. Each storage may include a plurality of first storage groups in a first area and a plurality of second storage groups in a second area. The first area may support physical addressing. The second area may not support physical addressing. A memory controller of the memory system may perform a wear leveling process by swapping a first storage group having a first group write count with a second storage group having a second group write count. The first group write count may be a maximum group write count among a plurality of group write counts corresponding to the plurality of first storage groups. The second group write count may be a minimum group write count among a plurality of group write counts corresponding to the plurality of second storage groups.

Abstract: The present disclosure provides a memory system with a non-volatile memory that includes a plurality of storage areas. Each storage may include a plurality of first storage groups in a first area and a plurality of second storage groups in a second area. The first area may support physical addressing. The second area may not support physical addressing. A memory controller of the memory system may perform a wear leveling process by swapping a first storage group having a first group write count with a second storage group having a second group write count. The first group write count may be a maximum group write count among a plurality of group write counts corresponding to the plurality of first storage groups. The second group write count may be a minimum group write count among a plurality of group write counts corresponding to the plurality of second storage groups.

Abstract: A method for a memory system is disclosed. The memory system can include a memory controller and a memory device. The method can include receiving data that includes bits and is to be written into the memory device, counting a first bit number of the bits corresponding to a first state and a second bit number of the bits corresponding to the second state, and in response to the second bit number of the bits being larger than the first bit number of the bits, the flipping operation is performed.

Abstract: A method for a memory system is disclosed. The memory system can include a memory controller and a memory device. The method can include receiving data that includes bits and is to be written into the memory device, counting a first bit number of the bits corresponding to a first state and a second bit number of the bits corresponding to the second state, and in response to the second bit number of the bits being larger than the first bit number of the bits, the flipping operation is performed.

Abstract: The present disclosure involves methods, apparatuses, and computer-readable storage media for media scan in a memory system. In one example, a method for a memory system includes receiving commands from a host coupled to the memory system, wherein the memory system includes a memory device, the memory device includes a memory cell array, and the memory cell array includes a number of memory cells. The method further includes performing operations on the memory device based on the commands. The method further includes scanning at least a group of memory cells of the memory cell array by performing a number of scans within a scan period among the operations.

Abstract: In certain aspects, a method for operating a non-volatile memory device is provided. The non-volatile memory device includes memory units. A write count of a first memory unit of the memory units is determined. In response to the write count of the first memory unit reaching one of preset values, a flipped bit count (FBC) of a second memory unit of the memory units that is physically adjacent to the first memory unit is obtained. In response to the FBC of the second memory unit exceeding a threshold, the second memory unit is refreshed.

Abstract: In certain aspects, a memory system includes a non-volatile memory device and a memory controller coupled to the non-volatile memory device. The non-volatile memory device includes a plurality of memory groups. Each of the memory groups includes a plurality of memory units. The memory controller is configured to perform at least one of a first wear-leveling process by swapping a first memory group of the memory groups and a second memory group of the memory groups based on a first group write count for the first memory group and a second group write count for the second memory group, or a second wear-leveling process by swapping a first memory unit of the memory units and a second memory unit of the memory units based on a first unit write count for the first memory unit and a second unit write count for the second memory unit.

Abstract: In an example, a memory controller is configured to: check whether a logical block address corresponding to a host read command is maintained in a write buffer; determine a level of an amount of drift corresponding to the logical block address if the logical block address is not maintained in the write buffer, where different levels of the amount of drift correspond to different read voltages; and send a read command to a non-volatile memory device according to the level of the amount of drift corresponding to the logical block address. At least two of the processes of checking whether the logical block address is maintained, determining the level of the amount of drift, or sending the read command are performed in parallel.

Abstract: An example memory controller and readable storage medium are disclosed. An example memory system includes: a non-volatile memory device and a memory controller coupled to the non-volatile memory device; the memory controller is configured to: determine whether data for the logical block address mapping of a received read command belongs to tables of a first class or tables of a second class, and confirm the heat of the data corresponding to the logical block address of the received read command; determine a level of the amount of drift of a threshold voltage of a memory cell corresponding to the logical block address, according to the heat of the data corresponding to the logical block address of the received read command; determine different read voltages that are correspondingly sent to the memory cell corresponding to the logical block address, according to different levels of the amount of drift.