Abstract: A light source driver circuit is provided that has at least first and second current source circuits that are electrically coupled to a node of the driver circuit. The first and second current source circuits source first and second fractions, respectively, of a total current needed to drive a light source into a node of the driver circuit. The driver circuit uses a sum of the first and second fractions of the total current in combination with a modulation current to drive the light source. By incorporating at least first and second current source circuits into the driver circuit, each of the current sources can be kept sufficiently small in size that they contribute very little parasitic capacitance, and therefore allow the driver circuit to achieve high-bandwidth operations while also allowing the driver circuit to operate at a low supply voltage.

Abstract: A TIA circuit is provided that utilizes current steering to adjust the gain of a TIA of the TIA circuit. As the optical input power of the optoelectronic (OE) detector that is coupled to the input of the TIA increases, the gain of the TIA is decreased via current steering, and as the optical input power of the OE detector decreases, the gain of the TIA is increased via current steering. Utilizing current steering to adjust the gain of the TIA allows the TIA circuit to have a configuration that has reduced power consumption compared to TIA circuits that use shunt feedback TIAs. In addition the TIA circuit configuration provides reduced peaking, improved linearization and high bandwidth.

Abstract: A CDR circuit for use in an optical receiver is provided that performs automatic rate negotiation. The CDR circuit is configured to determine whether the incoming data signal has a first, second or third data rate. If the CDR circuit determines that the incoming data signal has the first data rate, the CDR circuit places itself in a bypass mode of operations so that CDR is not performed. If the CDR circuit determines that the incoming data signal has the second or third data rates, the CDR circuit places itself in a CDR mode of operations and performs CDR on the incoming data signal.

Abstract: A TIA circuit is provided that utilizes current steering to adjust the gain of a TIA of the TIA circuit. As the optical input power of the optoelectronic (OE) detector that is coupled to the input of the TIA increases, the gain of the TIA is decreased via current steering, and as the optical input power of the OE detector decreases, the gain of the TIA is increased via current steering. Utilizing current steering to adjust the gain of the TIA allows the TIA circuit to have a configuration that has reduced power consumption compared to TIA circuits that use shunt feedback TIAs. In addition the TIA circuit configuration provides reduced peaking, improved linearization and high bandwidth.

Abstract: A control device that may be implemented in a single IC chip is provided that is capable of controlling EAM bias voltages and DFB bias currents and of monitoring the EAM photocurrents and received signal strength indicators (RSSIs) in a multi-channel optical transceiver module. The control device IC chip can be manufactured at relatively low cost with relatively high yield, and can be implemented in a relatively small area. To implement the control device in a single IC chip, multiple supply voltage domains are used in the IC chip, one of which is a negative supply voltage domain and one of which is a positive supply voltage domain. In order to provide these different supply voltage domains, a level shift circuit is employed in the IC chip that converts signals from the positive to the negative supply voltage domain, and vice versa, and changes the voltage levels, as needed.

Abstract: A control device that may be implemented in a single IC chip is provided that is capable of controlling EAM bias voltages and DFB bias currents and of monitoring the EAM photocurrents and received signal strength indicators (RSSIs) in a multi-channel optical transceiver module. The control device IC chip can be manufactured at relatively low cost with relatively high yield, and can be implemented in a relatively small area. To implement the control device in a single IC chip, multiple supply voltage domains are used in the IC chip, one of which is a negative supply voltage domain and one of which is a positive supply voltage domain. In order to provide these different supply voltage domains, a level shift circuit is employed in the IC chip that converts signals from the positive to the negative supply voltage domain, and vice versa, and changes the voltage levels, as needed.

Abstract: A light source driver circuit is provided that has at least first and second current source circuits that are electrically coupled to a node of the driver circuit. The first and second current source circuits source first and second fractions, respectively, of a total current needed to drive a light source into a node of the driver circuit. The driver circuit uses a sum of the first and second fractions of the total current in combination with a modulation current to drive the light source. By incorporating at least first and second current source circuits into the driver circuit, each of the current sources can be kept sufficiently small in size that they contribute very little parasitic capacitance, and therefore allow the driver circuit to achieve high-bandwidth operations while also allowing the driver circuit to operate at a low supply voltage.

Abstract: A burst-mode TIA circuit for use in PON receivers is provided that supports multiple data rates, has high receiver sensitivity, wide dynamic range, and that performs burst-mode synchronization very quickly. The multi-rate burst-mode TIA circuit has a high-speed data path that has low input-referred noise. Based on the chosen data rate at which the multi-rate burst-mode TIA circuit will operate, the rate select switch selects an appropriate feedback resistor of the resistive feedback network.

Abstract: A burst-mode TIA circuit for use in PON receivers is provided that supports multiple data rates, has high receiver sensitivity, wide dynamic range, and that performs burst-mode synchronization very quickly. The multi-rate burst-mode TIA circuit has a high-speed data path that has low input-referred noise. Based on the chosen data rate at which the multi-rate burst-mode TIA circuit will operate, the rate select switch selects an appropriate feedback resistor of the resistive feedback network.

Abstract: A CDR circuit for use in an optical receiver is provided that performs automatic rate negotiation. The CDR circuit is configured to determine whether the incoming data signal has a first, second or third data rate. If the CDR circuit determines that the incoming data signal has the first data rate, the CDR circuit places itself in a bypass mode of operations so that CDR is not performed. If the CDR circuit determines that the incoming data signal has the second or third data rates, the CDR circuit places itself in a CDR mode of operations and performs CDR on the incoming data signal.

Abstract: An amplifier, a circuit, and an optical communication system are provided. The disclosed amplifier may include a single-to-differential variable gain amplifier having a variable resistor switch that substantially always operates in a triode region at all time. Said another way, the resistor switch is configured to operate in a triode region regardless of whether or not a first portion of an input signal to the variable gain amplifier is larger than a second portion of the input signal. The disclosed scheme helps to keep the variable resistor switch in the triode region in all cases of operation, thereby maintaining the linearity condition and reducing distortion in the variable gain amplifier.

Abstract: An amplifier, a circuit, and an optical communication system are provided. The disclosed amplifier may include a first transistor receiving a first portion of an input signal received at the amplifier, a second transistor receiving a second portion of the input signal, an automatic gain control signal that is dynamically adjustable in response to variations in an output of the amplifier, and a varactor that has its capacitance adjusted by changes in the automatic gain control signal and, as a result, adjusts a position of a pole in a transfer function of the amplifier.

Abstract: A digitally-controlled transimpedance amplifier (TIA) circuit is provided in which a plurality of feedback loops are digitally controlled, including, but not limited to, the DC offset cancellation loop, the variable gain control loop, and the TIA feedback impedance adjustment loop. The digitally-controlled TIA circuit includes digital loop-control circuitry that consumes less area on the TIA IC chip than the analog circuitry traditionally used to perform the feedback loop control in the analog domain. In addition, because digital logic continues to shrink as IC processes continue to evolve, the size of the IC chip packages will further decrease over time, leading to a smaller footprint in systems in which they are employed. The digital loop control circuitry is also capable of independently varying the gains of multiple gain stages of the variable gain control circuit to provide better control over the gain stages and better overall performance of the TIA circuit.

Abstract: A digitally-controlled transimpedance amplifier (TIA) circuit is provided in which a plurality of feedback loops are digitally controlled, including, but not limited to, the DC offset cancellation loop, the variable gain control loop, and the TIA feedback impedance adjustment loop. The digitally-controlled TIA circuit includes digital loop-control circuitry that consumes less area on the TIA IC chip than the analog circuitry traditionally used to perform the feedback loop control in the analog domain. In addition, because digital logic continues to shrink as IC processes continue to evolve, the size of the IC chip packages will further decrease over time, leading to a smaller footprint in systems in which they are employed. The digital loop control circuitry is also capable of independently varying the gains of multiple gain stages of the variable gain control circuit to provide better control over the gain stages and better overall performance of the TIA circuit.

Abstract: Each channel of a high speed multi-channel transmitter or receiver IC chip layout is partitioned into at least first and second channel portions that are electrically interconnected with one another. Each first channel portion has an end that is located on an optical interface side of the multi-channel transmitter or receiver IC chip. Each second channel portion has an end that is located on an electrical interface side of the multi-channel transmitter or receiver IC chip. The pitch between the first channel portions is very fine and matches the pitch between optoelectronic elements of an optoelectronic array chip that interfaces with the optical interface side of the multi-channel transmitter or receiver IC chip. The pitch between the second channel portions is significantly greater than the pitch between the first channel portions to prevent cross talk.

Abstract: An optical communication system, circuit, and Integrated Circuit (IC) chip are disclosed. The disclosed optical communication system includes a photodiode configured to receive light energy and convert the light energy into an electrical signal, an amplifier configured to receive the electrical signal from the photodiode and output an amplified electrical signal, and a control circuit comprising a biasing network that generates a modular logic level that scales with a bias voltage of the photodiode.

Abstract: Each channel of a high speed multi-channel transmitter or receiver IC chip layout is partitioned into at least first and second channel portions that are electrically interconnected with one another. Each first channel portion has an end that is located on an optical interface side of the multi-channel transmitter or receiver IC chip. Each second channel portion has an end that is located on an electrical interface side of the multi-channel transmitter or receiver IC chip. The pitch between the first channel portions is very fine and matches the pitch between optoelectronic elements of an optoelectronic array chip that interfaces with the optical interface side of the multi-channel transmitter or receiver IC chip. The pitch between the second channel portions is significantly greater than the pitch between the first channel portions to prevent cross talk.

Abstract: High-speed PRBS-N pattern generator, error detector and error counter circuits are provided that have relatively simple circuit configurations, that quickly synchronize and align the input data with the generated pattern, that easily and quickly detect the occurrence of a bit shifting event, and that quickly resynchronize and realign the input data with the generated pattern after a bit shifting event has occurred. The error counter may be implemented with low-speed circuitry even though the pattern generator and error detector operate at the same speed as the high-speed input data signal. This reduces the complexity and power consumption of the error counter.

Abstract: An optical communication system, a linear optical receiver, and an Integrated Circuit (IC) chip are disclosed, among other things. One example of the disclosed IC chip includes a transimpedance amplifier that receives an input electrical signal from a photodiode and provides an amplified version of the input electrical signal as an output, at least one variable gain amplifier that receives the amplified electrical signal output by the transimpedance amplifier and a bandwidth control mechanism that extends a bandwidth of the second amplified output at a maximum gain of the second amplification phase and also reduces a peaking of the second amplified output at a minimum gain of the second amplification phase.

Abstract: An amplifier, a circuit, and an optical communication system are provided. The disclosed amplifier may include a first transistor receiving a first portion of an input signal received at the amplifier, a second transistor receiving a second portion of the input signal, an automatic gain control signal that is dynamically adjustable in response to variations in an output of the amplifier, and a varactor that has its capacitance adjusted by changes in the automatic gain control signal and, as a result, adjusts a position of a pole in a transfer function of the amplifier.