Patents by Inventor Faquir C. Jain

Faquir C. Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10820845
    Abstract: An analyte monitoring platform consisting of a proximity communicator and an implantable biosensor that includes system architecture for biosensor authentication, identification and methods to use analyte sensors for general wellness. The system architecture also permits multi-analyte sensing. In addition, the system and methods can be used for a single analyte or combination of analytes.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: November 3, 2020
    Assignee: Biorasis, Inc.
    Inventors: Fotios Papadimitrakopoulos, Antonio Costa, Faquir C. Jain, Michael Kastellorizios
  • Publication number: 20180064382
    Abstract: An analyte monitoring platform consisting of a proximity communicator and an implantable biosensor that includes system architecture for biosensor authentication, identification and methods to use analyte sensors for general wellness. The system architecture also permits multi-analyte sensing. In addition, the system and methods can be used for a single analyte or combination of analytes.
    Type: Application
    Filed: September 5, 2017
    Publication date: March 8, 2018
    Inventors: Fotios Papadimitrakopoulos, Antonio Costa, Faquir C. Jain, Michael Kastellorizios
  • Patent number: 9509400
    Abstract: An implantable bio-sensing platform architecture that enables the wireless selection, calibration and reading of multiple sensors, as well as checking the power levels of the solar powering source energizing various electronic and optoelectronic devices and circuits embedded in the platform. It also permits checking the operation of the potentiostats interfacing with each amperometric analyte sensor. The platform is flexible to include FET based sensors for protein sensing as well as other applications including pH sensing. In addition, other physiological sensors can be integrated in the platform.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: November 29, 2016
    Inventors: Faquir C Jain, Fotios Papadimitrakopoulos, Robert A Croce, Jr., Pawan Gogna, Syed Kamrul Islam, Liang Zuo, Kai Zhu
  • Publication number: 20160254863
    Abstract: An implantable bio-sensing platform architecture that enables the wireless selection, calibration and reading of multiple sensors, as well as checking the power levels of the solar powering source energizing various electronic and optoelectronic devices and circuits embedded in the platform. It also permits checking the operation of the potentiostats interfacing with each amperometric analyte sensor. The platform is flexible to include FET based sensors for protein sensing as well as other applications including pH sensing. In addition, other physiological sensors can be integrated in the platform.
    Type: Application
    Filed: May 9, 2016
    Publication date: September 1, 2016
    Inventors: Faquir C. Jain, Fotios Papadimitrakopoulos, Robert A. Croce, JR., Pawan Gogna, Syed Kamrul Islam, Liang Zuo, Kai Zhu
  • Patent number: 9337924
    Abstract: An implantable bio-sensing platform architecture that enables the wireless selection, calibration and reading of multiple sensors, as well as checking the power levels of the solar powering source energizing various electronic and optoelectronic devices and circuits embedded in the platform. It also permits checking the operation of the potentiostats interfacing with each amperometric analyte sensor. The platform is flexible to include FET based sensors for protein sensing as well as other applications including pH sensing. In addition, other physiological sensors can be integrated in the platform.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: May 10, 2016
    Inventor: Faquir C. Jain
  • Patent number: 9331209
    Abstract: The present invention discloses structures and method of fabricating cladded quantum dot gate nonvolatile memory and three-state field-effect transistor devices that can be scaled down to sub-22 nm dimensions and embedded along side with other functional circuits. Another innovation is the design of transport channel, which comprises an asymmetric coupled well structure comprising two or more wells. This structure enhances the retention time in nonvolatile memory by increasing the effective separation between channel charge and the quantum dots located in the floating gate. The cladded quantum dot gate FETs can be designed in Si, InGaAs—InP and other material systems. The 3-state FET devices form the basis of novel digital circuits using multiple valued logic and advanced analog circuits. One or more layers of SiOx-cladded Si quantum dots can also be used as high-k dielectric layer forming the gate insulator over the transport channel of a sub-22 nm FET.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: May 3, 2016
    Inventor: Faquir C Jain
  • Patent number: 9166363
    Abstract: Structures and methodologies to obtain lasing in indirect gap semiconductors such as Ge and Si are provided and involves excitonic transitions in the active layer comprising of at least one indirect gap layer. Excitonic density is increased at a given injection current level by increasing their binding energy by the use of quantum wells, wires, and dots with and without strain. Excitons are formed by holes and electrons in two different layers that are either adjacent or separated by a thin barrier layer, where at least one layer confining electrons and holes is comprised of indirect gap semiconductor such as Si and Ge, resulting in high optical gain and lasing using optical and electrical injection pumping.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: October 20, 2015
    Inventor: Faquir C. Jain
  • Patent number: 9153594
    Abstract: The present invention discloses use of quantum dot gate FETs as a nonvolatile memory element that can be used in flash memory architecture as well as in a nonvolatile random access memory (NVRAM) configuration that does not require refreshing of data as in dynamic random access memories. Another innovation is the design of quantum dot gate nonvolatile memory and 3-state devices using modulation doped field-effect transistors (MODFETs), particularly MOS-gate field effect transistors. The cladded quantum dot gate MODFETs can be designed in Si—SiGe, InGaAs—InP and other material systems. The incorporation of 3-state FET devices in static random access memory (SRAM) cell is described to result in advanced multi-state memory operation. Unlike conventional SRAMs, the 3-state QD-FET based of SRAMs provides 3 and 4-state memory operation due to the utilization of the intermediate states particularly in CMOS configuration.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: October 6, 2015
    Inventor: Faquir C. Jain
  • Publication number: 20150238118
    Abstract: A methodology used to pinpoint the location of an implantable biomedical sensing device is provided and is carried out by integrating miniaturized magnets, or materials with magnetic properties into the implantable bio-sensing chip to detect the position of the implant by sensing the induced magnetic field via an external communication unit. Presented here are various configurations in which magnetic positional detection can be carried out. The positional information collected from these detection motifs can be used to provide feedback to the user about alignment status as well as activate a self-alignment methodology. With respect to the former, based on the positional information received the user manually adjusts the location of the external communicator into place to align with the implantable platform.
    Type: Application
    Filed: March 20, 2014
    Publication date: August 27, 2015
    Inventors: Allen Legassey, Robert A. Croce, JR., Santhisagar Vaddiraju, Faquir C. Jain, Fotios Papadimitrakopoulos
  • Patent number: 8853667
    Abstract: Quantum dot (QD) gate FETs and the use of quantum dot (QD) gate FETs for the purpose of sensing analytes and proteins is disclosed and described. Analytes, proteins, miRNAs, and DNAs functionalized to the QDs change the charge density in the gate and hence the current-voltage characteristics. In one embodiment, QD-FETs, such as 3-state configurations, the binding of chemical and biological species change the drain current-gate voltage characteristics resulting in detection. In one embodiment, DNA sensing is done by its binding to an existing reference DNA functionalized on to quantum dots which are located in the gate region of the FET.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: October 7, 2014
    Inventor: Faquir C. Jain
  • Publication number: 20140185640
    Abstract: Structures and methodologies to obtain lasing in indirect gap semiconductors such as Ge and Si are provided and involves excitonic transitions in the active layer comprising of at least one indirect gap layer. Excitonic density is increased at a given injection current level by increasing their binding energy by the use of quantum wells, wires, and dots with and without strain. Excitons are formed by holes and electrons in two different layers that are either adjacent or separated by a thin barrier layer, where at least one layer confining electrons and holes is comprised of indirect gap semiconductor such as Si and Ge, resulting in high optical gain and lasing using optical and electrical injection pumping. In other embodiment, structures are described where excitons formed in an active layer confining electrons in the direct gap layer and holes in the indirect gap layer; where layers are adjacent or separated by a thin barrier layer.
    Type: Application
    Filed: December 31, 2013
    Publication date: July 3, 2014
    Inventor: Faquir C. Jain
  • Patent number: 8698226
    Abstract: Disclosed herein is a device comprising a source region, a drain region and a gate layer; the source region, the drain region and the gate layer being disposed on a semiconductor host; the gate layer being disposed between source and drain regions; the gate layer comprising a first gate-insulator layer; a gate layer comprising carbon nanotubes and/or graphene. Disclosed herein too is a method comprising disposing a source region, a drain region and a gate layer on a semiconductor host; the gate layer being disposed between the source region and the drain region; the gate layer comprising carbon nanotubes and/or graphene.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: April 15, 2014
    Assignee: University of Connecticut
    Inventors: Faquir C. Jain, Fotios Papadimitrakopoulos
  • Publication number: 20140072308
    Abstract: An implantable bio-sensing platform architecture that enables the wireless selection, calibration and reading of multiple sensors, as well as checking the power levels of the solar powering source energizing various electronic and optoelectronic devices and circuits embedded in the platform. It also permits checking the operation of the potentiostats interfacing with each amperometric analyte sensor. The platform is flexible to include FET based sensors for protein sensing as well as other applications including pH sensing. In addition, other physiological sensors can be integrated in the platform.
    Type: Application
    Filed: September 10, 2013
    Publication date: March 13, 2014
    Applicants: The University of Tennessee, Knoxville, The University of Connecticut
    Inventor: Faquir C. Jain
  • Publication number: 20130140518
    Abstract: Quantum dot (QD) gate FETs and the use of quantum dot (QD) gate FETs for the purpose of sensing analytes and proteins is disclosed and described. Analytes, proteins, miRNAs, and DNAs functionalized to the QDs change the charge density in the gate and hence the current-voltage characteristics. In one embodiment, QD-FETs, such as 3-state configurations, the binding of chemical and biological species change the drain current-gate voltage characteristics resulting in detection. In one embodiment, DNA sensing is done by its binding to an existing reference DNA functionalized on to quantum dots which are located in the gate region of the FET.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 6, 2013
    Inventor: Faquir C. Jain
  • Publication number: 20100025660
    Abstract: Disclosed herein is a device comprising a source region, a drain region and a gate layer; the source region, the drain region and the gate layer being disposed on a semiconductor host; the gate layer being disposed between source and drain regions; the gate layer comprising a first gate-insulator layer; a gate layer comprising carbon nanotubes and/or graphene. Disclosed herein too is a method comprising disposing a source region, a drain region and a gate layer on a semiconductor host; the gate layer being disposed between the source region and the drain region; the gate layer comprising carbon nanotubes and/or graphene.
    Type: Application
    Filed: July 31, 2009
    Publication date: February 4, 2010
    Applicant: UNIVERSITY OF CONNECTICUT
    Inventors: Faquir C. Jain, Fotios Papadimitrakopoulos
  • Publication number: 20090184346
    Abstract: The present invention discloses structures and method of fabricating cladded quantum dot gate nonvolatile memory and three-state field-effect transistor devices that can be scaled down to sub-22 nm dimensions and embedded along side with other functional circuits. Another innovation is the design of transport channel, which comprises an asymmetric coupled well structure comprising two or more wells. This structure enhances the retention time in nonvolatile memory by increasing the effective separation between channel charge and the quantum dots located in the floating gate. The cladded quantum dot gate FETs can be designed in Si, InGaAs—InP and other material systems. The 3-state FET devices form the basis of novel digital circuits using multiple valued logic and advanced analog circuits. One or more layers of SiOx-cladded Si quantum dots can also be used as high-k dielectric layer forming the gate insulator over the transport channel of a sub-22 nm FET.
    Type: Application
    Filed: January 9, 2008
    Publication date: July 23, 2009
    Inventor: Faquir C. Jain
  • Publication number: 20090173934
    Abstract: The present invention discloses use of quantum dot gate FETs as a nonvolatile memory element that can be used in flash memory architecture as well as in a nonvolatile random access memory (NVRAM) configuration that does not require refreshing of data as in dynamic random access memories. Another innovation is the design of quantum dot gate nonvolatile memory and 3-state devices using modulation doped field-effect transistors (MODFETs), particularly MOS-gate field effect transistors. The cladded quantum dot gate MODFETs can be designed in Si—SiGe, InGaAs—InP and other material systems. The incorporation of 3-state FET devices in static random access memory (SRAM) cell is described to result in advanced multi-state memory operation. Unlike conventional SRAMs, the 3-state QD-FET based of SRAMs provides 3 and 4-state memory operation due to the utilization of the intermediate states particularly in CMOS configuration.
    Type: Application
    Filed: March 20, 2008
    Publication date: July 9, 2009
    Inventor: Faquir C. Jain
  • Patent number: 7368370
    Abstract: Disclosed herein are methods of self-assembling nanoparticles on specific sites of a substrate. The method generally includes introducing a p-type dopant species to at least a portion of an n-type substrate or introducing an n-type dopant species to at least a portion of a p-type substrate, wherein the dopant species creates a surface charge opposite in polarity to that of the substrate surface prior to the introducing; contacting the nanoparticles with the surface of the substrate; and self-assembling a layer of the nanoparticles on p-type regions of the substrate. The methods described herein may be used in the formation of sub-22 nanometer channels, which find use in field-effect transistors, electronic chips, nanoscale biosensors, photonic band gap devices, lasers in optoelectronics and photonics chips, as well as nano-electro-mechanical devices (NEMS).
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: May 6, 2008
    Assignee: The University of Connecticut
    Inventors: Faquir C. Jain, Fotios Papadimitrakopoulos
  • Publication number: 20080070354
    Abstract: Disclosed herein are methods of self-assembling nanoparticles on specific sites of a substrate. The method generally includes introducing a p-type dopant species to at least a portion of an n-type substrate or introducing an n-type dopant species to at least a portion of a p-type substrate, wherein the dopant species creates a surface charge opposite in polarity to that of the substrate surface prior to the introducing; contacting the nanoparticles with the surface of the substrate; and self-assembling a layer of the nanoparticles on p-type regions of the substrate. The methods described herein may be used in the formation of sub-22 nanometer channels, which find use in field-effect transistors, electronic chips, nanoscale biosensors, photonic band gap devices, lasers in optoelectronics and photonics chips, as well as nano-electro-mechanical devices (NEMS).
    Type: Application
    Filed: June 15, 2006
    Publication date: March 20, 2008
    Inventors: Faquir C. Jain, Fotios Papadimitrakopoulos
  • Patent number: 7326303
    Abstract: This invention describes an apparatus, Scanning Localized Evaporation Methodology (SLEM) for the close proximity deposition of thin films with high feature definition, high deposition rates, and significantly improved material economy. An array of fixed thin film heating elements, each capable of being individually energized, is mounted on a transport mechanism inside a vacuum chamber. The evaporable material is deposited on a heating element. The SLEM system loads the surface of heating elements, made of foils, with evaporable material. The loaded thin film heating element is transported to the substrate site for re-evaporation. The re-evaporation onto a substrate, which is maintained at the desired temperature, takes place through a mask. The mask, having patterned openings dictated by the structural requirements of the fabrication, may be heated to prevent clogging of the openings. The translation of the substrate past the evaporation site permits replication of the pattern over its entire surface.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: February 5, 2008
    Assignee: Optoelectronics Systems Consulting Inc.
    Inventors: Fotios Papadimitrakopoulos, Thomas Samuel Phely-Bobin, Daniel Harrison Grantham, deceased, Faquir C Jain