Abstract: Presented is a “high-order” Leading Zeros Anticipator or LZA circuit and specifically a five-input LZA. The prior-art two-input LZA circuit is part of almost all high-performance floating-point units or FPUs. The advantages of a high-order LZA (such as five-input) is that the LZA function may be started and finished sooner in the floating point pipeline, and therefore allows more time for other functions in the pipeline. Therefore, a high-order LZA, such as five-input LZA, may be faster than the prior art two-input LZA designs. Thus, speeding up the LZA function in a floating point pipeline may significantly increase the speed in which the overall floating-point unit may operate as compared to the prior-art two input LZA designs and may additionally inspire new floating-point michroarchitectures which may yield further performance gains.

Abstract: An apparatus for generating an end-around carry to an end-around carry adder in a floating-point pipeline within a computer system is disclosed. The apparatus for generating an end-around carry includes a shift-comparison logic circuit, a sign-comparison circuit, and a logic gate. The shift-comparison logic circuit produces a shift-count signal and the sign-comparison logic circuit produces an effective operation signal. Coupled to the shift-comparison logic circuit and the sign-comparison logic circuit, the logic gate combines the shift-count signal and the effective operation signal with a carry-out signal generated by an end-around carry adder to provide an end-around carry signal for the end-around carry adder.