Patents by Inventor Faraz Siddiqi
Faraz Siddiqi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11307868Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for receiving information to invoke a transition from a first operating system to a second operating system, copying a system context for the second operating system from a location of a non-volatile memory to a volatile memory, the location associated with the second operating system and transitioning from the first operating system to the second operating system using the system context for the second operating system.Type: GrantFiled: June 30, 2017Date of Patent: April 19, 2022Assignee: INTEL CORPORATIONInventors: Faraz A. Siddiqi, Barnes Cooper
-
Patent number: 10482278Abstract: A system for securing electronic devices includes a storage device including a storage device controller processor, at least one non-transitory machine readable storage medium in firmware of the storage device communicatively coupled to the storage device controller processor, and a monitor application comprising computer-executable instructions on the medium. The instructions are readable by the storage device controller processor. The monitor application is configured to provision one or more read-only areas of the storage device, provision a candidate copy area of the storage device, reduce a maximum capacity available for user data on the storage device by a size of the read-only areas and the candidate copy area, and secure access to the read-only areas of the storage device.Type: GrantFiled: March 8, 2019Date of Patent: November 19, 2019Assignee: McAfee, LLCInventors: Adrian R. Pearson, Sergiu D. Ghetie, Thomas R. Bowen, Gamil A. Cain, Jason Cox, Faraz A. Siddiqi, Neeraj S. Upasani
-
Publication number: 20190205560Abstract: A system for securing electronic devices includes a storage device including a storage device controller processor, at least one non-transitory machine readable storage medium in firmware of the storage device communicatively coupled to the storage device controller processor, and aa monitor application comprising computer-executable instructions on the medium. The instructions are readable by the storage device controller processor. The monitor application is configured to provision one or more read-only areas of the storage device, provision a candidate copy area of the storage device, reduce a maximum capacity available for user data on the storage device by a size of the read-only areas and the candidate copy area, and secure access to the read-only areas of the storage device.Type: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Inventors: Adrian R. Pearson, Sergiu D. Ghetie, Thomas R. Bowen, Gamil A. Cain, Jason Cox, Faraz A. Siddiqi, Neeraj S. Upasani
-
Patent number: 10229281Abstract: A system for securing electronic devices includes a storage device including a storage device controller processor, at least one non-transitory machine readable storage medium in firmware of the storage device communicatively coupled to the storage device controller processor, and a monitor application comprising computer-executable instructions on the medium. The instructions are readable by the storage device controller processor. The monitor application is configured to provision one or more read-only areas of the storage device, provision a candidate copy area of the storage device, reduce a maximum capacity available for user data on the storage device by a size of the read-only areas and the candidate copy area, and secure access to the read-only areas of the storage device.Type: GrantFiled: April 1, 2016Date of Patent: March 12, 2019Assignee: McAfee, LLCInventors: Adrian R. Pearson, Sergiu D. Ghetie, Thomas R. Bowen, Gamil A. Cain, Jason Cox, Faraz A. Siddiqi, Neeraj S. Upasani
-
Patent number: 9934047Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for receiving information to invoke a transition from a first operating system to a second operating system, copying a system context for the second operating system from a location of a non-volatile memory to a volatile memory, the location associated with the second operating system and transitioning from the first operating system to the second operating system using the system context for the second operating system.Type: GrantFiled: March 20, 2014Date of Patent: April 3, 2018Assignee: INTEL CORPORATIONInventors: Faraz A. Siddiqi, Barnes Cooper
-
Publication number: 20170359333Abstract: Generally, this disclosure provides devices, systems, methods and computer readable media for context based switching to a secure OS environment including cloud based data synchronization and filtration. The device may include a storage controller to provide access to the secure OS stored in an initially provisioned state; a context determination module to monitor web site access, classify a transaction between the device and the website and identify a match between the web site and a list of web sites associated with secure OS operation or a match between the transaction classification and a list of transaction types associated with secure OS operation; and an OS switching module to switch from a main OS to the secure OS in response to the identified match. The switch may include updating state data associated with the secure OS, the state data received from a secure cloud-based data synchronization server.Type: ApplicationFiled: August 1, 2017Publication date: December 14, 2017Applicant: Intel CorporationInventors: Faraz A. Siddiqi, Jasmeet Chhabra
-
Publication number: 20170300342Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for receiving information to invoke a transition from a first operating system to a second operating system, copying a system context for the second operating system from a location of a non-volatile memory to a volatile memory, the location associated with the second operating system and transitioning from the first operating system to the second operating system using the system context for the second operating system.Type: ApplicationFiled: June 30, 2017Publication date: October 19, 2017Applicant: INTEL CORPORATIONInventors: FARAZ A. SIDDIQI, BARNES COOPER
-
Patent number: 9753519Abstract: Methods and systems may include a human interface device (HID) and logic to place the HID in a blocked state in response to a request to power off the system. The logic can also use a speculative start-up heuristic to establish one or more subsequent operating states for the system while the HID is in the blocked state, wherein the background automatic state transitions may maximize battery life when a user is not present. In addition, the HID may be removed from the blocked state in response to a request to power on the system. Accordingly, the speculative start-up heuristic can make system “ready-to-use” before the user actually interacts with any inputs (e.g. power button, or touch screen) of the system.Type: GrantFiled: October 14, 2011Date of Patent: September 5, 2017Assignee: Intel CorporatoinInventors: Antonio S. Cheng, Faraz A. Siddiqi
-
Patent number: 9671971Abstract: Provided are a method, system, and computer readable storage medium for managing access to a storage device. A logical-to-physical mapping indicates for each logical address a physical address in the storage device having current data for the logical address and version information indicating whether there is a prior version of data for the logical address. In response to the logical-to-physical mapping indicating that there is no prior version of the data for a target logical address of a write, including information on the target physical address and the physical address indicated in the logical-to-physical mapping in checkpoint information. The version information for the target logical address is updated to indicate that there is a prior version of data. Data for the write is written to a target physical address. The logical-to-physical mapping for the target logical address is updated to indicate the target physical address.Type: GrantFiled: March 27, 2015Date of Patent: June 6, 2017Assignee: INTEL CORPORATIONInventors: Sanjeev N. Trika, Benjamin W. Boyer, Ravi L. Sahita, Xiaoning Li, Faraz A. Siddiqi
-
Publication number: 20170111388Abstract: A system for securing electronic devices includes a processor, a storage medium communicatively coupled to the processor, and a secured storage communicatively coupled to the client. The system further includes a client application including computer-executable instructions on the medium. The instructions are readable by the processor. The application is configured to manage a trusted image of software of a client in a secured storage and, upon a signal indicating malware on the client, restore the trusted image to the client independent of an operating system and user processes of the client.Type: ApplicationFiled: April 1, 2016Publication date: April 20, 2017Inventors: Kunal Mehta, Dmitri Rubakha, Carl D. Woodward, Steven L. Grobman, Adrian R. Pearson, Faraz A. Siddiqi
-
Publication number: 20170103225Abstract: A system for securing electronic devices includes a storage device including a storage device controller processor, at least one non-transitory machine readable storage medium in firmware of the storage device communicatively coupled to the storage device controller processor, and a monitor application comprising computer-executable instructions on the medium. The instructions are readable by the storage device controller processor. The monitor application is configured to provision one or more read-only areas of the storage device, provision a candidate copy area of the storage device, reduce a maximum capacity available for user data on the storage device by a size of the read-only areas and the candidate copy area, and secure access to the read-only areas of the storage device.Type: ApplicationFiled: April 1, 2016Publication date: April 13, 2017Inventors: Adrian R. Pearson, Sergiu D. Ghetie, Thomas R. Bowen, Gamil A. Cain, Jason Cox, Faraz A. Siddiqi, Neeraj S. Upasani
-
Patent number: 9507402Abstract: With embodiments of the invention, a more robust solution is provided using a storage driver that may already be used for the platforms operating system. This is efficient because the storage driver typically already monitors storage drive access requests, and thus knows when traffic is outstanding (performance may be critical) or when it's not outstanding (and power may be saved).Type: GrantFiled: November 26, 2013Date of Patent: November 29, 2016Assignee: Intel CorporationInventors: Barnes Cooper, Faraz A. Siddiqi
-
Patent number: 9494998Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, at least one graphics engine to independently execute graphics instructions, and a power controller including an alignment logic to cause at least one workload to be executed on a first core to be rescheduled to a different time to enable the plurality of cores to be active during an active time window and to be in a low power state during an idle time window. Other embodiments are described and claimed.Type: GrantFiled: December 17, 2013Date of Patent: November 15, 2016Assignee: Intel CorporationInventors: Inder M. Sodhi, Barnes Cooper, Paul S. Diefenbaugh, Faraz A. Siddiqi, Michael Calyer, Andrew D. Henroid, Ruchika Singh
-
Publication number: 20160283160Abstract: Provided are a method, system, and computer readable storage medium for managing access to a storage device. A logical-to-physical mapping indicates for each logical address a physical address in the storage device having current data for the logical address and version information indicating whether there is a prior version of data for the logical address. In response to the logical-to-physical mapping indicating that there is no prior version of the data for a target logical address of a write, including information on the target physical address and the physical address indicated in the logical-to-physical mapping in checkpoint information. The version information for the target logical address is updated to indicate that there is a prior version of data. Data for the write is written to a target physical address. The logical-to-physical mapping for the target logical address is updated to indicate the target physical address.Type: ApplicationFiled: March 27, 2015Publication date: September 29, 2016Inventors: Sanjeev N. TRIKA, Benjamin W. BOYER, Ravi L. SAHITA, Xiaoning LI, Faraz A. SIDDIQI
-
Patent number: 9436251Abstract: Fast platform hibernation and resumption for computing systems. An embodiment of an apparatus includes a volatile system memory, a nonvolatile memory, and a processor to operate according to an operating system, the processor to transition the apparatus to a first reduced power state upon receipt of a request, the transition to the first reduced power state including the processor to store context information for the computer in the volatile system memory.Type: GrantFiled: October 1, 2011Date of Patent: September 6, 2016Assignee: Intel CorporeationInventors: Barnes Cooper, Faraz A. Siddiqi
-
Publication number: 20150268968Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for receiving information to invoke a transition from a first operating system to a second operating system, copying a system context for the second operating system from a location of a non-volatile memory to a volatile memory, the location associated with the second operating system and transitioning from the first operating system to the second operating system using the system context for the second operating system.Type: ApplicationFiled: March 20, 2014Publication date: September 24, 2015Inventors: Faraz A. Siddiqi, Barnes Cooper
-
Publication number: 20150169036Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, at least one graphics engine to independently execute graphics instructions, and a power controller including an alignment logic to cause at least one workload to be executed on a first core to be rescheduled to a different time to enable the plurality of cores to be active during an active time window and to be in a low power state during an idle time window. Other embodiments are described and claimed.Type: ApplicationFiled: December 17, 2013Publication date: June 18, 2015Inventors: Inder M. Sodhi, Barnes Cooper, Paul S. Diefenbaugh, Faraz A. Siddiqi, Michael Calyer, Andrew D. Henroid, Ruchika Singh
-
Patent number: 9032139Abstract: Memory allocation for fast platform hibernation and resumption of computing systems. An embodiment of an apparatus includes logic at least partially implemented in hardware, the logic to: dynamically allocate at least a first portion of a nonvolatile memory; in response to a command to enter the apparatus into a standby state, the logic to store at least a portion of a context data from a volatile memory to the dynamically allocated first portion of the nonvolatile memory; and in response to a resumption of operation of the apparatus, the logic to copy at least the portion of the context data from the first portion of the nonvolatile memory to the volatile memory, and to reclaim the first portion of the nonvolatile memory for dynamic allocation.Type: GrantFiled: December 28, 2012Date of Patent: May 12, 2015Assignee: Intel CorporationInventors: Faraz A. Siddiqi, Francis R. Corrado, Barnes Cooper
-
Patent number: 8984316Abstract: Secure fast platform hibernation and resumption for computing systems. An embodiment of an apparatus includes a processor to operate according to an operating system, the processor to transition the apparatus to a first reduced power state in response to a request, the transition to the first reduced power state including the processor to store context data for the apparatus in a volatile system memory, and logic to transition the apparatus to a second reduced power state, the logic to write the context data from the volatile system memory to a nonvolatile memory for the transition to the second reduced power state, wherein the logic is to implement one or more security measures for the writing of the context data into the nonvolatile memory.Type: GrantFiled: December 29, 2011Date of Patent: March 17, 2015Assignee: Intel CorporationInventors: Jeff Forristal, Faraz Siddiqi, Lukasz Mielicki, Hao-Chi Wong
-
Publication number: 20140337918Abstract: Generally, this disclosure provides devices, systems, methods and computer readable media for context based switching to a secure OS environment including cloud based data synchronization and filtration. The device may include a storage controller to provide access to the secure OS stored in an initially provisioned state; a context determination module to monitor web site access, classify a transaction between the device and the website and identify a match between the web site and a list of web sites associated with secure OS operation or a match between the transaction classification and a list of transaction types associated with secure OS operation; and an OS switching module to switch from a main OS to the secure OS in response to the identified match. The switch may include updating state data associated with the secure OS, the state data received from a secure cloud-based data synchronization server.Type: ApplicationFiled: March 14, 2013Publication date: November 13, 2014Inventors: Faraz A. Siddiqi, Jasmeet Chhabra