Abstract: Methods for operating a substrate processing cluster tool include positioning a substrate storage cassette within a factory interface of the substrate processing cluster tool, wherein the substrate storage cassette defines an interior volume dimensioned and arranged to receive one or more substrates, and sensing, by execution of stored instructions by a processor operatively associated with a plurality of sensors, at least one of occurrence of a condition of a plurality of conditions within the interior volume or persistence of a condition of the plurality of conditions within the interior volume. Responsive to the sensing, at least one of generating an alert or performing an alternate operation involving the substrate storage cassette.

Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

Abstract: Methods for operating a substrate processing cluster tool include positioning a substrate storage cassette within a factory interface of the substrate processing cluster tool, wherein the substrate storage cassette defines an interior volume dimensioned and arranged to receive one or more substrates, and sensing, by execution of stored instructions by a processor operatively associated with a plurality of sensors, at least one of occurrence of a condition of a plurality of conditions within the interior volume or persistence of a condition of the plurality of conditions within the interior volume. Responsive to the sensing, at least one of generating an alert or performing an alternate operation involving the substrate storage cassette.

Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

Abstract: In one embodiment, a method for etching a substrate includes providing a reactive ambient around the substrate when a non-crystalline layer is disposed over a first crystalline material in the substrate; generating a plasma in a plasma chamber; modifying a shape of a plasma sheath boundary of the plasma; extracting ions from the plasma; and directing the ions to the substrate at a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate, wherein the ions and reactive ambient are effective to form an angled cavity through the non-crystalline layer to expose a portion of the first crystalline material at a bottom of the angled cavity, and the angled cavity forms a non-zero angle of inclination with respect to the perpendicular.

Abstract: In one embodiment, a method for etching a substrate includes providing a reactive ambient around the substrate when a non-crystalline layer is disposed over a first crystalline material in the substrate; generating a plasma in a plasma chamber; modifying a shape of a plasma sheath boundary of the plasma; extracting ions from the plasma; and directing the ions to the substrate at a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate, wherein the ions and reactive ambient are effective to form an angled cavity through the non-crystalline layer to expose a portion of the first crystalline material at a bottom of the angled cavity, and the angled cavity forms a non-zero angle of inclination with respect to the perpendicular.

Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

Abstract: Embodiments of the present disclosure generally relate to doping and annealing substrates. The substrates may be doped during a hot implantation process, and subsequently annealed using a nanosecond annealing process. The combination of hot implantation and nanosecond annealing reduces lattice damage of the substrates and facilitates a higher dopant concentration near the surface of the substrate to facilitate increased electrical contact with the substrate. An optional capping layer may be placed over the substrate to reduce outgassing of dopants or to control dopant implant depth.

Abstract: In one embodiment a method of forming low contact resistance in a substrate includes forming a silicide layer on the substrate, the silicide layer and substrate defining an interface therebetween in a source/drain region, and performing a hot implant of a dopant species into the silicide layer while the substrate is at a substrate temperature greater than 150° C., where the hot implant is effective to generate an activated dopant layer containing the dopant species, and the activated dopant layer extends from the interface into the source/drain region.

Abstract: In one embodiment a method of forming low contact resistance in a substrate includes forming a silicide layer on the substrate, the silicide layer and substrate defining an interface therebetween in a source/drain region, and performing a hot implant of a dopant species into the silicide layer while the substrate is at a substrate temperature greater than 150° C., where the hot implant is effective to generate an activated dopant layer containing the dopant species, and the activated dopant layer extends from the interface into the source/drain region.

Abstract: An improved method of creating LED arrays is disclosed. A p-type layer, multi-quantum well and n-type layer are disposed on a substrate. The device is then etched to expose portions of the n-type layer. To create the necessary electrical isolation between adjacent LEDs, an ion implantation is performed to create a non-conductive implanted region. In some embodiments, an implanted region extends through the p-type layer, MQW and n-type layer. In another embodiment, a first implanted region is created in the n-type layer. In addition, a second implanted region is created in the p-type layer and multi-quantum well immediately adjacent to etched n-type layer. In some embodiments, the ion implantation is done perpendicular to the substrate. In other embodiments, the implant is performed at an angle.

Abstract: A lateral light emitting diode comprises a layer stack disposed on one side of a substrate, the layer stack including a p-type layer, n-type layer, and a p/n junction formed therebetween. The LED may further include a p-electrode disposed on a first side of the substrate and being in contact with the p-type layer on an exposed surface and an n-electrode disposed on the first side of the substrate and being in contact with an exposed surface of an n+ sub-layer of the n-type layer.

Abstract: An improved method of creating LED arrays is disclosed. A p-type layer, multi-quantum well and n-type layer are disposed on a substrate. The device is then etched to expose portions of the n-type layer. To create the necessary electrical isolation between adjacent LEDs, an ion implantation is performed to create a non-conductive implanted region. In some embodiments, an implanted region extends through the p-type layer, MQW and n-type layer. In another embodiment, a first implanted region is created in the n-type layer. In addition, a second implanted region is created in the p-type layer and multi-quantum well immediately adjacent to etched n-type layer. In some embodiments, the ion implantation is done perpendicular to the substrate. In other embodiments, the implant is performed at an angle.

Abstract: A lateral light emitting diode comprises a layer stack disposed on one side of a substrate, the layer stack including a p-type layer, n-type layer, and a p/n junction formed therebetween. The LED may further include a p-electrode disposed on a first side of the substrate and being in contact with the p-type layer on an exposed surface and an n-electrode disposed on the first side of the substrate and being in contact with an exposed surface of an n+ sub-layer of the n-type layer.