Abstract: A system includes a plurality of content addressable memory (CAM) arrays and a plurality of logic circuits which are connected to a commonly shared bus. Each CAM array provides search results (hit, match address and multiple match) in a search operation in response to a clock signal. Hit, match address and multiple match signals are provided from the CAM arrays to the logic circuits which are associated with the CAM arrays. The hit signals provided from the CAM arrays are propagated from upstream to downstream logic circuits in response to a self-timed signal which is delayed in time from the clock signal. The logic circuits prevent more than one match address signal provided from the CAM array from being transferred simultaneously to the commonly shared bus. The multiple match signals provided from the CAM arrays are propagated from upstream to downstream logic circuits.

Abstract: A system includes a plurality of content addressable memory (CAM) arrays and a plurality of logic circuits. The logic circuits are connected to a commonly shared bus. Each of the logic circuits is associated with the respective CAM array. Each of the CAM arrays provides search results (hit, match address and multiple match) in a search operation in response to a clock signal. The hit signals provided from the CAM arrays to the respective logic circuits. Each logic circuit provides an OR logic output signal from a hit signal input from an upstream logic circuit and the hit signal provided by the CAM array associated with that logic circuit, in response to a self-timed signal which is delayed in time from the clock signal. The OR logic output signal provided by the logic circuit is provided to a downstream logic circuit. Thus, the furthest downstream logic circuit provides a hit result of the system in a search operation.

Abstract: A content addressable memory employs a word-sliced architecture, in order to localize word match logic, and a global data bus, to convey data between the memory input/output circuitry and the plurality of word slices. Timing information is embedded in the global data bus in the form of a model global data signal. This signal interacts with two major control signals to self-time the memory. The number of major control signals is such that all possible memory states are uniquely represented, but the memory cannot power-up in an invalid or unrecoverable state. Three model timing paths are used to match the delay of the self-timing loop with that of the actual operation: one each for READ, WRITE and SEARCH.

Abstract: The implementation of two-dimensional decoding, necessary to achieve a reasonable array aspect ratio for a large content addressable memory, is achieved by having multiple match lines per physical row, these match lines being physically routed on top of the array core cell in an upper metal layer. To limit power dissipation in the resulting large-capacity content addressable memory, the match function is implemented by two or more NAND chains per word. Means for achieving the precharging and evaluation of these chains, and for implementing dummy chains for the provision of timing information, are also disclosed.