Patents by Inventor Farhad Zarkeshvari

Farhad Zarkeshvari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240007264
    Abstract: Transceiver array synchronization by receiving a clock signal and at least one synchronization pulse signal at each transceiver IC of a plurality of transceiver integrated circuit (IC) subarrays, wherein each transceiver IC subarray contains a respective set of serially connected transceiver ICs; and synchronizing the transceiver IC with other transceiver ICs of the respective set of serially connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state in accordance with the received at least one synchronization pulse signal.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 4, 2024
    Inventors: Claudio Anzil, Yang Xu, Farhad Zarkeshvari
  • Patent number: 7940098
    Abstract: A phase-locked loop includes a phase-to-digital converter that receives a first periodic input signal at a first input and a first feedback signal at a second input. The phase-to-digital converter generates digital signals. A digitally controlled oscillator includes a delay-locked loop that is responsive to the digital signals. The delay-locked loop generates a periodic output signal having an average frequency that is a product of a frequency of the first periodic input signal multiplied by a non-integer fractional number while a phase of the first periodic input signal is unchanging.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: May 10, 2011
    Assignee: Altera Corporation
    Inventors: Tad Kwasniewski, Farhad Zarkeshvari
  • Patent number: 7675332
    Abstract: Phase detection circuitry in a delay-locked loop compares a periodic input signal to a feedback signal. The phase detection circuitry generates a delay signal that controls delays of the delay circuits. Two or more output signals of the delay circuits are transmitted to an input of the phase detection circuitry. The delay-locked loop can be configured so that the period of the periodic input signal divided by a delay of one of the delay circuits equals a non-integer rational number when the phase and frequency of the periodic input signal are constant. A frequency multiplier can be coupled to the delay circuits to generate a periodic output signal. The periodic output signal has an average frequency that is a product of the frequency of the periodic input signal multiplied by a fractional non-integer number when the phase and frequency of the periodic input signal are constant.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: March 9, 2010
    Assignee: Altera Corporation
    Inventors: Tad Kwasniewski, Farhad Zarkeshvari