Patents by Inventor Farhana Sheikh

Farhana Sheikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9852540
    Abstract: Disclosed is an apparatus and method for generating a lighting value based on a number of lighting factors. A lighting accelerator first converts an ambient portion, a diffuse light portion, and a specular light portion of the lighting factors into the log domain. Then, data combination units operate on the lighting factors after they have been converted. Then, the lighting factors are converted back from the log domain using anti-log processing. Converting the lighting factors into the log domain is accomplished by using a series of linear equations using coefficients that are all based on powers of two, and are therefore easily calculable. Further, while in the log domain, the specular light portion of the lighting factor is operated on by a special purpose multiplier that uses a truncated partial product tree, saving area and power with only a negligible amount of error.
    Type: Grant
    Filed: December 31, 2011
    Date of Patent: December 26, 2017
    Assignee: Intel Corporation
    Inventors: Farhana Sheikh, Sanu Mathew, Ram Krishnamurthy
  • Patent number: 9843352
    Abstract: The disclosure generally relates to a method, apparatus and system for identifying non-compliant radio emissions and for enforcing compliance. In one embodiment, the disclosure relates to a dynamic radiation control of a radio by measuring a signal attribute for an outbound signal having a protocol; comparing the signal attribute with a predefined mask, the predefined mask governed by at least one of a radio location or a signal protocol; and determining whether to transmit the outbound signal.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: December 12, 2017
    Assignee: Intel Corporation
    Inventors: Hossein Alavi, Farhana Sheikh, Markus Dominik Mueck, Vladimir Ivanov
  • Publication number: 20170288747
    Abstract: Embodiments relate to systems, methods, and computer readable media to enable a wireless receiver are described. In one embodiment a wireless receiver includes a channel decoder and a Soft-Input Soft-Output Multiple-Input Multiple-Output detector (SISO MIMO detector). The SISO MIMO detector includes circuitry to generate soft symbol outputs for each of a plurality of received spatial streams, and circuitry to adjust a signal to noise plus interference ratio for the soft symbol outputs using channel statistics and using hard decisions from an output of the channel decoder. The channel decoder is configured to receive soft binary information generated from the soft symbol outputs from the SISO MIMO detector and perform these steps iteratively a number of times.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 5, 2017
    Inventors: CHIA-HSIANG CHEN, MOHAMED K. HASSANIN, AHMED GAMAL HELMY MOHAMED, SHAHRNAZ AZIZI, FARHANA SHEIKH, ASSAF GUREVITZ, THOMAS J. KENNEY
  • Patent number: 9698838
    Abstract: A receiver system includes a blocker detector circuit configured to receive a radio frequency (RF) input signal and detect an existence of a blocker therein, and further configured to output a blocker detection signal indicative of the existence of the blocker. The receiver system further includes a configurable receiver circuit configured to receive the RF input signal and the blocker detection signal, and selectively configure the configurable receiver circuit between a first mode wherein the configurable receiver circuit exhibits first linearity characteristics, and a second mode wherein the configurable receiver circuit exhibits second, different linearity characteristics based on the blocker detection signal.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Shreyas Sen, Ritesh Bhat, Yanjie Wang, Stefano Pellerano, Christopher Hull, Farhana Sheikh
  • Publication number: 20170187405
    Abstract: A receiver system includes a blocker detector circuit configured to receive a radio frequency (RF) input signal and detect an existence of a blocker therein, and further configured to output a blocker detection signal indicative of the existence of the blocker. The receiver system further includes a configurable receiver circuit configured to receive the RF input signal and the blocker detection signal, and selectively configure the configurable receiver circuit between a first mode wherein the configurable receiver circuit exhibits first linearity characteristics, and a second mode wherein the configurable receiver circuit exhibits second, different linearity characteristics based on the blocker detection signal.
    Type: Application
    Filed: December 23, 2015
    Publication date: June 29, 2017
    Inventors: Shreyas Sen, Ritesh Bhat, Yanjie Wang, Stefano Pellerano, Christopher Hull, Farhana Sheikh
  • Publication number: 20170085252
    Abstract: An adaptation hardware accelerator comprises a calculation unit configured to receive a plurality of inputs at one or more predefined time intervals, wherein each time interval corresponds to a calculation iteration, the plurality of inputs being associated with a plurality of adaptive filters each having a plurality of taps, and determine a correlation data and a cross-correlation data based thereon for a given calculation iteration. The correlation data comprises a correlation matrix comprising a plurality of sub-matrices, wherein determining the correlation matrix comprises determining only the submatrices in an upper triangular portion and a diagonal portion of the correlation matrix. Further, the adaptation hardware accelerator comprises an adaptation core unit configured to determine a plurality of adaptive weights associated with the plurality of adaptive filters, respectively, based on an optimized RLS based adaptive algorithm, by utilizing the correlation data and the cross correlation data.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 23, 2017
    Inventors: Farhana Sheikh, Ching-En Lee, Feng Xue, Anuja S. Vaidya, Eduardo X. Alban, Albert Oskar Filip Andersson, Chia-Hsiang Chen, Shu-Ping Yeh
  • Patent number: 9584164
    Abstract: A mixer-first receiver operates to generate filtering and analog-to-digital conversion concurrently and adaptively, while removing an LNA before a mixer to enable integration with digital baseband circuits. A plurality of switching capacitor arrays are integrated with a hybrid analog-to-digital filtering component. Switching capacitor arrays of the plurality of switching capacitor arrays can be selectively modified to perform both the filtering operation and the conversion operation together. The same switch capacitors of a switching capacitor array can be utilized in one phase of a clock cycle for the filtering and in another phase of the clock cycle for the conversion.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: February 28, 2017
    Assignee: Intel Corporation
    Inventors: Farhana Sheikh, Amy L. Whitcombe, Erkan Alpman, Yanjie Wang, Shreyas Sen
  • Patent number: 9544133
    Abstract: Methods and apparatus to provide on-the-fly key computation for Galois Field (also referred to Finite Field) encryption and/or decryption are described. In one embodiment, logic generates a cipher key, in a second cycle, based on a previous cipher key, generated in a first cycle that immediately precedes the second cycle. Other embodiments are also described.
    Type: Grant
    Filed: December 26, 2009
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventors: Sanu K. Mathew, Farhana Sheikh, Ram K. Krishnamurthy, Michael E. Kounavis, Shay Gueron
  • Publication number: 20160380653
    Abstract: A polynomial kernel generator is configured to mitigate nonlinearity in a receiver path from a transmitter path comprising a nonlinear component in a communication device or system. The polynomial kernel generator operates to generate polynomial kernels that can be utilized to model the nonlinearity as a function of a piecewise polynomial approximation applied to a nonlinear function of the nonlinearity. The polynomial kernel generator generates kernels in a multiplier less architecture with polynomial computations in a log domain using a fixed number of adders.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: Farhana Sheikh, Ching-En Lee, Shu-Ping Yeh, Feng Xue, Anuja Surendra Vaidya
  • Publication number: 20160379694
    Abstract: In some embodiments, disclosed is a wordline boosting technique using a self-timed capacitive charge boosting approach.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Applicant: Intel Corporation
    Inventors: JAYDEREP KULKARNI, PRAMOD KOLAR, ANKIT SHARMA, SUBHO CHATTERJEE, KARTHIK SUBRAMANIAN, FARHANA SHEIKH, WEI-HSIANG MA
  • Publication number: 20160248464
    Abstract: The disclosure generally relates to a method, apparatus and system for identifying non-compliant radio emissions and for enforcing compliance. In one embodiment, the disclosure relates to a dynamic radiation control of a radio by measuring a signal attribute for an outbound signal having a protocol; comparing the signal attribute with a predefined mask, the predefined mask governed by at least one of a radio location or a signal protocol; and determining whether to transmit the outbound signal.
    Type: Application
    Filed: December 26, 2013
    Publication date: August 25, 2016
    Inventors: Hossein ALAVI, Farhana SHEIKH, Markus Dominik Mueck, Vladimir IVANOV
  • Patent number: 9225521
    Abstract: Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventors: Farhana Sheikh, Jesse Walker, Sanu K. Mathew, Ram K. Krishnamurthy
  • Publication number: 20150023500
    Abstract: Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.
    Type: Application
    Filed: October 6, 2014
    Publication date: January 22, 2015
    Inventors: Farhana Sheikh, Jesse Walker, Sanu K. Mathew, Ram K. Krishnamurthy
  • Patent number: 8855302
    Abstract: Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: October 7, 2014
    Assignee: Intel Corporation
    Inventors: Farhana Sheikh, Jesse Walker, Sanu K. Mathew, Ram Krishnamurthy
  • Publication number: 20140028677
    Abstract: Disclosed is an apparatus and method for generating a lighting value based on a number of lighting factors. A lighting accelerator first converts an ambient portion, a diffuse light portion, and a specular light portion of the lighting factors into the log domain. Then, data combination units operate on the lighting factors after they have been converted. Then, the lighting factors are converted back from the log domain using anti-log processing. Converting the lighting factors into the log domain is accomplished by using a series of linear equations using coefficients that are all based on powers of two, and are therefore easily calculable. Further, while in the log domain, the specular light portion of the lighting factor is operated on by a special purpose multiplier that uses a truncated partial product tree, saving area and power with only a negligible amount of error.
    Type: Application
    Filed: December 31, 2011
    Publication date: January 30, 2014
    Applicant: Intel Corporation
    Inventors: Farhana Sheikh, Sanu Mathew, Ram Krishnamurthy
  • Publication number: 20120328097
    Abstract: Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.
    Type: Application
    Filed: June 21, 2011
    Publication date: December 27, 2012
    Inventors: Farhana Sheikh, Jesse Walker, Sanu K. Mathew, Ram Krishnamurthy
  • Publication number: 20110158403
    Abstract: Methods and apparatus to provide on-the-fly key computation for Galois Field (also referred to Finite Field) encryption and/or decryption are described. In one embodiment, logic generates a cipher key, in a second cycle, based on a previous cipher key, generated in a first cycle that immediately precedes the second cycle. Other embodiments are also described.
    Type: Application
    Filed: December 26, 2009
    Publication date: June 30, 2011
    Inventors: Sanu K. Mathew, Farhana Sheikh, Ram K. Krishnamurthy, Michael E. Kounavis, Shay Gueron
  • Patent number: 7860240
    Abstract: A system comprises reception of input data of a Galois field GF(2k), mapping of the input data to a composite Galois field GF(2nm), where k=nm, inputting of the mapped input data to an Advanced Encryption Standard round function, performance of two or more iterations of the Advanced Encryption Standard round function in the composite Galois field GF(2nm), reception of output data of a last of the two or more iterations of the Advanced Encryption Standard round function, and mapping of the output data to the Galois field GF(2k).
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: December 28, 2010
    Assignee: Intel Corporation
    Inventors: Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy
  • Publication number: 20090003589
    Abstract: A system comprises reception of input data of a Galois field GF(2k), mapping of the input data to a composite Galois field GF(2nm), where k=nm, inputting of the mapped input data to an Advanced Encryption Standard round function, performance of two or more iterations of the Advanced Encryption Standard round function in the composite Galois field GF(2nm), reception of output data of a last of the two or more iterations of the Advanced Encryption Standard round function, and mapping of the output data to the Galois field GF(2k).
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy