Abstract: An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load.

Abstract: An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load.

Abstract: An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load.

Abstract: A circuit provides a voltage reference using very low power. It can also be used as a shut regulator for a quiescent current as low as 1.5 ?A. It includes a transconductance amplifier, a gain stage, and a power transistor. One embodiment of this invention utilizes a work function difference between p+ gate and n+ gate to generate a predetermined reference voltage. In another embodiment of this invention, the predetermined reference voltage can be pre-adjusted using gate materials with different work functions.

Abstract: An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load.

Abstract: An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load.

Abstract: An error amplifier expected to exhibit rail-to-rail operation, high bandwidth, and high slew rate, is described, the error amplifier comprising a first stage to receive an input differential voltage and to provide transconductance gain, an intermediate stage to provide current gain, and an output stage to drive a load.

Abstract: A circuit provides a voltage reference using very low power. It can also be used as a shut regulator for a quiescent current as low as 1.5?A. It includes a transconductance amplifier, a gain stage, and a power transistor. One embodiment of this invention utilizes a work function difference between p+ gate and n+ gate to generate a predetermined reference voltage. In another embodiment of this invention, the predetermined reference voltage can be pre-adjusted using gate materials with different work functions.

Abstract: The present invention provides a method and apparatus for dynamically correcting overshoot and undershoot errors in an analog integrated circuit by improving the reaction time (?t) of the analog integrated circuit. Equivalently, an error correction circuit is disclosed present invention is only activated to reduce overshoot and undershoot errors by increasing the bandwidth of the integrated circuit when either undershoot or overshoot errors are detected.

Abstract: A circuit provides a voltage reference using very low power. It can also be used as a shut regulator for a quiescent current as low as 1.5 ?A. It includes a transconductance amplifier, a gain stage, and a power transistor. One embodiment of this invention utilizes a work function difference between p+ gate and n+ gate to generate a predetermined reference voltage. In another embodiment of this invention, the predetermined reference voltage can be pre-adjusted using gate materials with different work functions.

Abstract: Methods and apparatus are disclosed for providing stable voltage references from within a low dropout voltage regulator. Some embodiments utilize dependable semiconductor inherent attributes to generate a voltage reference, such as a band-gap voltage reference.

Abstract: The present invention provides a method and apparatus for dynamically correcting overshoot and undershoot errors in an analog integrated circuit by improving the reaction time (?t) of the analog integrated circuit. Equivalently, an error correction circuit is disclosed including an overshoot correction circuit and an undershoot correction circuit that are only activated to reduce overshoot and undershoot errors by increasing the bandwidth of the integrated circuit when either undershoot or overshoot errors are detected.

Abstract: The present invention provides a method and apparatus for dynamically correcting overshoot and undershoot errors in an analog integrated circuit by improving the reaction time (?t) of the analog integrated circuit. Equivalently, an error correction circuit is disclosed including an overshoot correction circuit and an undershoot correction that are only activated to reduce overshoot and undershoot errors by increasing the bandwidth of the integrated circuit when either undershoot or overshoot errors are detected.

Abstract: Methods and apparatus are disclosed for providing stable voltage references from within a low dropout voltage regulator. Some embodiments utilize dependable semiconductor inherent attributes to generate a voltage reference, such as a band-gap voltage reference.

Abstract: A circuit provides a voltage reference using very low power. It can also be used as a shut regulator for a quiescent current as low as 1.5 ?A. It includes a transconductance amplifier, a gain stage, and a power transistor. One embodiment of this invention utilizes a work function difference between p+ gate and n+ gate to generate a predetermined reference voltage. In another embodiment of this invention, the predetermined reference voltage can be pre-adjusted using gate materials with different work functions.

Abstract: A field effect transistor (FET) driver circuit includes an error amplifier for providing a FET control signal and a current limiting amplifier for preventing excessive current flow through the FET. The current limiting amplifier generates an overcurrent signal when an excessive current is detected. In response to the overcurrent signal, a voltage control circuit adjusts the voltage at the output of the error amplifier to turn off the FET. Meanwhile, a pulldown circuit at an input of the error amplifier adjusts the voltage provided to that input to cause the error amplifier to provide an output voltage that also tends to turn off the FET. If a buffer is present at that input to the error amplifier, a second pulldown circuit is placed at the input to the buffer to maintain a stable unity gain across the buffer.

Abstract: A current mirror includes a serially connected diode-connected transistor of a first conductivity type, a saturated (fully-on) transistor of a second conductivity type, and a current source for providing a reference current. A gate voltage generated by the diode-connected transistor in response to the reference current is provided to the gate of a matching transistor. This causes the matching transistor to mirror the reference current. Meanwhile, an output transistor cascoded with the matching transistor is gate-coupled to the junction between the saturated transistor and the current source. This allows the output transistor to provide an output voltage swing from one supply voltage to two saturation voltage drops from the second supply voltage. Meanwhile, the cascode configuration gives the current mirror a high output impedance.

Abstract: A field effect transistor (FET) driver circuit includes an error amplifier for providing a FET control signal and a current limiting amplifier for preventing excessive current flow through the FET. The current limiting amplifier generates an overcurrent signal when an excessive current is detected. In response to the overcurrent signal, a voltage control circuit adjusts the voltage at the output of the error amplifier to turn off the FET. Meanwhile, a pulldown circuit at an input of the error amplifier adjusts the voltage provided to that input to cause the error amplifier to provide an output voltage that also tends to turn off the FET. If a buffer is present at that input to the error amplifier, a second pulldown circuit is placed at the input to the buffer to maintain a stable unity gain across the buffer.

Abstract: A differential CMOS amplifier includes two CMOS inverters and biasing circuitry providing feedback loops across the output and input of each inverter. The biasing circuitry provides linear biasing so that the inverters can apply a desired gain to a pair of high frequency input signals (i.e., a differential input signal). The biasing circuitry can include operational amplifiers (op-amps) for providing positive feedback control between the output and input of the inverters. The inputs of the inverters can be regulated by this feedback loop such that their outputs are driven to the reference voltage, thereby forcing the inverters to operate in their linear regions so that non-distorting amplification can be applied to the input AC signals.

Abstract: A CMOS amplifier includes a CMOS inverter and a bias circuit coupled in a feedback loop between the output and input of the inverter. The bias circuit provides linear biasing so that the inverter can apply a desired gain to a high frequency input signal. The bias circuit can include an operational amplifier (op-amp) providing positive feedback control between the output and input of the inverter. By providing a reference voltage to the other input of the op-amp, the input of the inverter is regulated such that its output is driven to the reference voltage. This in turn forces the inverter to operate in its linear region, so that the inverter applies non-distorting amplification to the input AC signal. The AC signal is prevented from affecting the operation of the bias circuit by resistors coupling the bias circuit to the op-amp.