Patents by Inventor Fariborz Agahdel
Fariborz Agahdel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8531202Abstract: A probe card analyzer mounts on a probe card in a wafer prober and a use a fixture in the wafer probe and switch electronics in place of an ATE head. Methods of testing can confirm that probe cards are operating within their specifications over large temperature ranges and the mechanical force ranges seen in real manufacturing environments. This reduces the cost and improves the accuracy and speed of analyzing probe cards and improves diagnosing problems with probe cards.Type: GrantFiled: October 10, 2008Date of Patent: September 10, 2013Assignee: VeraConnex, LLCInventors: Sammy Mok, Frank Swiatowiec, Fariborz Agahdel
-
Patent number: 7876087Abstract: Probecard architectures partition the spring compliance required for IC testing between several different components. Such architectures can provide shorter springs, better impedance control, improved power/ground distribution and more direct paths to tester electronics. The probecards can also use thinner interconnector substrates to conform to the planarity of a DUT and may suspend such a substrate by wires attached to a perimeter edge of the substrate to permit the substrate to tilt. Tilting can also be facilitated by positioning tester-side springs away from the perimeter of the substrate. Low compliance MEMS probes for such architectures can be provided on replaceable coupons having attachment points away from electrical connections, and a method for fabricating probe springs can plate spring material on a membrane deformed by contact with a bumped substrate.Type: GrantFiled: September 12, 2007Date of Patent: January 25, 2011Assignee: Innoconnex, Inc.Inventors: Sammy Mok, Frank J. Swiatowiec, Fariborz Agahdel
-
Publication number: 20100213960Abstract: A probe card analyzer mounts on a probe card in a wafer prober and a use a fixture in the wafer probe and switch electronics in place of an ATE head. Methods of testing can confirm that probe cards are operating within their specifications over large temperature ranges and the mechanical force ranges seen in real manufacturing environments. This reduces the cost and improves the accuracy and speed of analyzing probe cards and improves diagnosing problems with probe cards.Type: ApplicationFiled: October 10, 2008Publication date: August 26, 2010Inventors: Sammy Mok, Frank Swiatowiec, Fariborz Agahdel
-
Publication number: 20080061808Abstract: Probecard architectures partition the spring compliance required for IC testing between several different components. Such architectures can provide shorter springs, better impedance control, improved power/ground distribution and more direct paths to tester electronics. The probecards can also use thinner interconnector substrates to conform to the planarity of a DUT and may suspend such a substrate by wires attached to a perimeter edge of the substrate to permit the substrate to tilt. Tilting can also be facilitated by positioning tester-side springs away from the perimeter of the substrate. Low compliance MEMS probes for such architectures can be provided on replaceable coupons having attachment points away from electrical connections, and a method for fabricating probe springs can plate spring material on a membrane deformed by contact with a bumped substrate.Type: ApplicationFiled: September 12, 2007Publication date: March 13, 2008Inventors: Sammy Mok, Frank Swiatowiec, Fariborz Agahdel
-
Patent number: 6937044Abstract: A bare semiconductor circuit die carrier is provided for use in the test of semiconductor circuits, the carrier, comprising: a substrate defining an opening and an outer perimeter; a multiplicity of I/O pads disposed about the perimeter; an interconnect circuit which includes a composite of a multiplicity of individual electrical conductors which are formed in a polymer dielectric; wherein the interconnect circuit overlays a top surface of the substrate and extends across the opening so as to form a flexible membrane that spans the opening; a multiplicity of die contact pads connected to the conductors are disposed about the flexible membrane with particles deposited on the die contact pads; a fence upstanding from the membrane and sized to receive a test die; a top cap that rests upon the die when the die is received within the fence; a bottom cap that rests against a bottom surface of the substrate; and a fastener for securing the top cap to the bottom cap with the die disposed therebetween.Type: GrantFiled: March 24, 2000Date of Patent: August 30, 2005Assignee: Kulicke & Soffa Industries, Inc.Inventors: Fariborz Agahdel, Brad Griswold, Syed Husain, Robert Moti, William C. Robinette, Jr., Chung W. Ho
-
Patent number: 6049215Abstract: A bare semiconductor circuit die carrier is provided for use in the test of semiconductor circuits, the carrier, comprising: a substrate defining an opening and an outer perimeter; a multiplicity of I/O pads disposed about the perimeter; an interconnect circuit which includes a composite of a multiplicity of individual electrical conductors which are formed in a polymer dielectric; wherein the interconnect circuit overlays a top surface of the substrate and extends across the opening so as to form a flexible membrane that spans the opening; a multiplicity of die contact pads connected to the conductors are disposed about the flexible membrane with particles deposited on the die contact pads; a fence upstanding from the membrane and sized to receive a test die; a top cap that rests upon the die when the die is received within the fence; a bottom cap that rests against a bottom surface of the substrate; and a fastener for securing the top cap to the bottom cap with the die disposed therebetween.Type: GrantFiled: October 12, 1995Date of Patent: April 11, 2000Assignee: Kulicke & Soffa Ind. Inc.Inventors: Fariborz Agahdel, Brad Griswold, Syed Husain, Robert Moti, William C. Robinette, Jr., Chung W. Ho
-
Patent number: 5468157Abstract: An interconnect system (8) for providing electrical connection to bond pads on a semiconductor device (21) includes a socket (12) having a plurality of conductors (46) with retractable contact portions (14) and a carrier assembly (40) mounted on the socket (12) for carrying a semiconductor device (21). The carrier assembly (40) includes a substrate (17) having a compliant membrane (20b), a plurality of contact bumps (24) containing oxide-penetrating particles on a top surface of the compliant membrane (20b) for contacting bond pads on the semiconductor device (21), a fence (30) attached to the top surface of the compliant membrane (20b) for positioning the semiconductor device (21) so that the bond pads on the semiconductor device (21) are aligned with the contact bumps (24). Compliant membrane (20b) is part of a thin film interconnect (20). Contact bumps (24) are connected electrically with conductors (46) by conductive traces (19) and contact pads (18) formed on the thin film interconnect (20).Type: GrantFiled: October 29, 1993Date of Patent: November 21, 1995Assignee: Texas Instruments IncorporatedInventors: Randal D. Roebuck, Fariborz Agahdel, Salvatore P. Rizzo
-
Patent number: 5402077Abstract: An integrated circuit carrier comprising: a substrate defining an opening and an outer perimeter; a multiplicity of I/O pads disposed about the perimeter; an interconnect circuit which includes a composite of a multiplicity of individual electrical conductors which are formed in a polymer dielectric; wherein the interconnect circuit overlays a top surface of the substrate and extends across the opening so as to span the opening; a multiplicity of die contact pads connected to the conductors are disposed about the flexible polymer dielectric with particles deposited on the die contact pads; a polymer dielectric fence upstanding from the membrane and sized to receive an integrated circuit; a top cap that rests upon the integrated circuit when the integrated circuit is received within the fence; a bottom cap that rests against a bottom surface of the substrate; and a fastener for securing the top cap to the bottom cap with the integrated circuit disposed therebetween.Type: GrantFiled: November 20, 1992Date of Patent: March 28, 1995Assignee: Micromodule Systems, Inc.Inventors: Fariborz Agahdel, Brad Griswold, Syed Husain, Robert Moti, William C. Robinette, Jr., Chung W. Ho
-
Patent number: 5267867Abstract: An integrated circuit package has multiple integrated circuits (ICs) mounted face down directly on one surface of a flexible circuit which is disposed in an opening of a rigid signal carrier, such as a pin grid array. The flexible circuit provides connections among the ICs, and also between the ICs and the signal carrier via wirebonds. The flexible circuit is attached to a rigid support ring that is bonded to the signal carrier adjacent to the opening. A thermally conductive lid covers the opening and contacts the backs of the ICs for heat removal. A rigid plate presses elastomeric pads against the other surface of the flexible circuit to maintain firm contact between the flexible circuit and the ICs and also between the ICs and the lid. The package may be hermetically sealed by attaching a cover to the support ring.Type: GrantFiled: September 11, 1992Date of Patent: December 7, 1993Assignee: Digital Equipment CorporationInventors: Fariborz Agahdel, Chung Wen Ho