Abstract: An integrated circuit selectively operable in either a first mode (consuming low power) or a second mode (consuming relatively high power). The circuit includes MOS transistors and a supply voltage circuit for at least one of the transistors. In both modes, the supply voltage circuit holds the body of each transistor at a fixed voltage (e.g., a voltage V.sub.CC in a range from 5 to 5.5 volts, where each transistor is a PMOS device). In the second mode the supply voltage circuit supplies this fixed voltage to the source of each transistor, but in the first mode it supplies a voltage equal to or slightly offset from the fixed voltage to the source of each transistor. In some embodiments, the supply voltage circuit (in the first mode, after an initial transient state) supplies a first voltage to a well shared by a plurality of PMOS transistors, and a second voltage to the source of each PMOS device.

Abstract: An integrated circuit operable in a test mode and a normal operating mode, which includes an improved test mode switch. In the test mode of preferred embodiments in which the circuit is an integrated memory chip, the test mode switch is closed so as to connect an input/output (I/O) pad directly with a selected memory cell (so a current/voltage characterization of the cell can be obtained). In the normal operating mode of these embodiments, the test mode switch is open and it isolates the I/O pad from direct connection with the selected cell even under the condition that a transistor of the test mode switch undesirably becomes conductive (e.g., due to low voltage on the I/O pad, inductive coupling, or the like).

Abstract: A method for verifying the status of selected nonvolatile memory cells of an integrated memory circuit, such as during a memory erase or programming operation, and an integrated nonvolatile memory circuit including circuitry for performing this verification method. Preferably, the invention employs simple logic circuitry including a flip-flop to assert successful verification data only in response to a continuous validity of a verification signal throughout a sampling period, thereby avoiding false assertion of successful verification data. The sampling period is preferably longer than the expected duration of fluctuations due to noise in the verification signal. During the sampling period of a verification operation, the logic circuitry receives a raw verification signal indicative of the instantaneous relation between a measured threshold voltage of a selected memory cell and a reference voltage.

Abstract: A circuit which responds to an external standby command (a transition in a chip enable signal from an external device) by generating a delayed internal standby signal. The internal standby signal functions by switching selected components of the circuit (such as address buffers) from an active mode to a standby mode. In preferred embodiments, the circuit is a memory circuit implemented as an integrated circuit. The amount of the delay in generating the delayed internal standby signal is selected to achieve a desired decreased average response time to a sequence of commands (such as memory access commands) without excessive power consumption. In embodiments in which the circuit is a memory chip (such as a flash memory chip) having address access time in the range from 60 ns to 80 ns, the delay typically is from about 100 ns to about 200 ns.