Abstract: The disclosure provides transistor cells for integrated circuits and methods to form the same. A transistor cell according to the disclosure may include a substrate region including width between a first end and a second end, and a length between a third end and a fourth end in a direction orthogonal to the width. A first doped well (FDW) within the substrate region may be oppositely doped and may extend from the first end to a first interior boundary between the first and second ends of the substrate region, and from the third end to a second interior boundary between the third and fourth ends. A second doped well (SDW) within the substrate region may extend from the second end to a third interior boundary between the first and second ends, and the fourth end to a fourth interior boundary between the third and fourth ends.

Abstract: The disclosure provides transistor cells for integrated circuits and methods to form the same. A transistor cell according to the disclosure may include a substrate region including width between a first end and a second end, and a length between a third end and a fourth end in a direction orthogonal to the width. A first doped well (FDW) within the substrate region may be oppositely doped and may extend from the first end to a first interior boundary between the first and second ends of the substrate region, and from the third end to a second interior boundary between the third and fourth ends. A second doped well (SDW) within the substrate region may extend from the second end to a third interior boundary between the first and second ends, and the fourth end to a fourth interior boundary between the third and fourth ends.

Abstract: A method for creating a design for an integrated circuit, by developing a set of delay cells where each of the cells in the set has a different delay time from the other cells in the set, and where each of the cells in the set has the same surface area, has the same pin-outs, has the same drive strength, and has the same input capacitance, where an originally-used cell in the set can be swapped out for a different replacement cell in the set without any impact on the design of the integrated circuit besides a change in delay time from the originally-used cell to the replacement cell.

Abstract: An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced.

Abstract: An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced.