Patents by Inventor Fariz A. Siddiqi

Fariz A. Siddiqi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030023812
    Abstract: A technique for computer initialization with caching includes enabling at least one cache memory and then copying an option BIOS from a first memory to a PAM (Programmable Attribute Map) main memory area, the copying including executing a cache-line fill to the at least one cache memory. Initialization is then performed by providing control to the option BIOS, the execution being performed substantially from the at least one cache memory. Processor MTRRs(Memory Type Range Registers) for the PAM memory area may be programmed as write-back. The at least one cache memory may be at least one of L1 and L2 processor cache memories. The first memory may be a flash memory or a ROM (Read Only Memory). The at least one cache memory may be flushed upon completion of the option BIOS execution.
    Type: Application
    Filed: June 19, 2001
    Publication date: January 30, 2003
    Inventors: Rajeev K. Nalawadi, Fariz A. Siddiqi