Abstract: Method and apparatus for redundant array of independent disks (RAID) recovery are disclosed. In one embodiment, a RAID controller schedules requests to rebuild failed drives based on the wear state of secondary drives and input/output (I/O) activity. The controller may be configured to assign higher scheduling priority to rebuild requests only when necessary, so as to reduce the time needed for the rebuild and to avoid affecting performance of the RAID system. In particular, the controller may give higher priority to rebuild requests if secondary drive failure is likely. In addition, the controller may determine when write-intensive periods occur, and assign lower priority to rebuild requests during such periods.

Abstract: Method and apparatus for redundant array of independent disks (RAID) recovery are disclosed. In one embodiment, a RAID controller schedules requests to rebuild failed drives based on the wear state of secondary drives and input/output (I/O) activity. The controller may be configured to assign higher scheduling priority to rebuild requests only when necessary, so as to reduce the time needed for the rebuild and to avoid affecting performance of the RAID system. In particular, the controller may give higher priority to rebuild requests if secondary drive failure is likely. In addition, the controller may determine when write-intensive periods occur, and assign lower priority to rebuild requests during such periods.

Abstract: Method and apparatus for redundant array of independent disks (RAID) recovery are disclosed. In one embodiment, a RAID controller schedules requests to rebuild failed drives based on the wear state of secondary drives and input/output (I/O) activity. The controller may be configured to assign higher scheduling priority to rebuild requests only when necessary, so as to reduce the time needed for the rebuild and to avoid affecting performance of the RAID system. In particular, the controller may give higher priority to rebuild requests if secondary drive failure is likely. In addition, the controller may determine when write-intensive periods occur, and assign lower priority to rebuild requests during such periods.

Abstract: Method and apparatus for redundant array of independent disks (RAID) recovery are disclosed. In one embodiment, a RAID controller schedules requests to rebuild failed drives based on the wear state of secondary drives and input/output (I/O) activity. The controller may be configured to assign higher scheduling priority to rebuild requests only when necessary, so as to reduce the time needed for the rebuild and to avoid affecting performance of the RAID system. In particular, the controller may give higher priority to rebuild requests if secondary drive failure is likely. In addition, the controller may determine when write-intensive periods occur, and assign lower priority to rebuild requests during such periods.

Abstract: A method for receiving a data packet is described. The method may include receiving a frame in a host Ethernet adapter from an Ethernet network. The frame may be parsed to determine a data packet size. A work queue element (WQE) may be selected from two or more available WQEs having different data packet size capacity. Data packet storage may be provided for each WQE, including at least some cache storage associated with a processor. The data packet may be stored in the data packet storage associated with the selected WQE based on the data packet size, including storing in the cache for data packets under selected conditions.

Abstract: A method for receiving a data packet is described. The method may include receiving a frame in a host Ethernet adapter from an Ethernet network. The frame may be parsed to determine a data packet size. A work queue element (WQE) may be selected from two or more available WQEs having different data packet size capacity. Data packet storage may be provided for each WQE, including at least some cache storage associated with a processor. The data packet may be stored in the data packet storage associated with the selected WQE based on the data packet size, including storing in the cache for data packets under selected conditions.

Abstract: A method for receiving a data packet is described. The method may include receiving a frame in a host Ethernet adapter from an Ethernet network. The frame may be parsed to determine a data packet size. A work queue element (WQE) may be selected from two or more available WQEs having different data packet size capacity. Data packet storage may be provided for each WQE, including at least some cache storage associated with a processor. The data packet may be stored in the data packet storage associated with the selected WQE based on the data packet size, including storing in the cache for data packets under selected conditions.

Abstract: Embodiments of the present invention generally provide techniques and apparatus to reduce the number of memory directory updates during block replacement in a system having a directory-based cache. The system may be implemented to utilize a read/write bit to determine the accessibility of a cache line and limit memory directory updates during block replacement to regions that are determined to be readable and writable by multiple processors.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design to reduce the number of memory directory updates during block replacement in a system having a directory-based cache is provided. The design structure may be implemented to utilize a read/write bit to determine the accessibility of a cache line and limit memory directory updates during block replacement to regions that are determined to be readable and writable by multiple processors.

Abstract: Embodiments of the present invention generally provide techniques and apparatus to reduce the number of memory directory updates during block replacement in a system having a directory-based cache. The system may be implemented to utilize a read/write bit to determine the accessibility of a cache line and limit memory directory updates during block replacement to regions that are determined to be readable and writable by multiple processors.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design to reduce the number of memory directory updates during block replacement in a system having a directory-based cache is provided. The design structure may be implemented to utilize a read/write bit to determine the accessibility of a cache line and limit memory directory updates during block replacement to regions that are determined to be readable and writable by multiple processors.

Abstract: A design structure of a speculative access mechanism in a memory subsystem monitors hit rate of an L1 cache, and autonomically switches modes of speculative accesses to an L2 cache accordingly. If the L1 hit rate is less than a threshold, such as 50%, the speculative load mode for the L2 cache is set to load-cancel. If the L1 hit rate is greater than or equal to the threshold, the speculative load mode for the L2 cache is set to load-confirm. By autonomically adjusting the mode of speculative accesses to an L2 cache as the L1 hit rate changes, the performance of a computer system that uses speculative accesses to an L2 cache improves.

Abstract: A speculative access mechanism in a memory subsystem monitors hit rate of an L1 cache, and autonomically switches modes of speculative accesses to an L2 cache accordingly. If the L1 hit rate is less than a threshold, such as 50%, the speculative load mode for the L2 cache is set to load-cancel. If the L1 hit rate is greater than or equal to the threshold, the speculative load mode for the L2 cache is set to load-confirm. By autonomically adjusting the mode of speculative accesses to an L2 cache as the L1 hit rate changes, the performance of a computer system that uses speculative accesses to an L2 cache improves.

Abstract: A multiprocessor computer system employs a number of levels of cache memories with each processor. A cache controller for a lower level cache memory receives a memory block pre-fetch request which requests a particular memory block. The cache controller determines a likelihood that the particular memory block will be invalidated prior to use of the memory block by a processor which issued the pre-fetch request. Based on that determination, the cache controller determines whether to honor the pre-fetch request.

Abstract: A multiprocessor computer system employs a number of levels of cache memories with each processor. A cache controller for a lower level cache memory receives a memory block pre-fetch request which requests a particular memory block. The cache controller determines a likelihood that the particular memory block will be invalidated prior to use of the memory block by a processor which issued the pre-fetch request. Based on that determination, the cache controller determines whether to honor the pre-fetch request.