Abstract: A semiconductor device manufacturing system is introduced. The system includes a carrier wafer, a first electrode layer disposed on the carrier wafer, a piezoelectric layer disposed on the first electrode layer, and a second electrode layer disposed on the piezoelectric layer. In addition, the system includes a device wafer having a bonding layer disposed on a surface of the device wafer, and a power source having a first terminal and a second terminal. The device wafer is bonded to the carrier wafer through the bonding layer, the first electrode layer, the piezoelectric layer, and the second electrode layer. The second electrode layer is configured to separate from the first electrode layer upon application of a bias voltage to the first and second electrode layers, and the device wafer is configured to debond from the carrier wafer through delaminating the piezoelectric layer from the first or second electrode layer.

Abstract: Electrolytic methods for carrier wafer separation are disclosed herein. In some embodiments, the method includes depositing a coating on a carrier wafer. The coating can include a first electrode layer, a second electrode layer, and a metal oxide layer between the first and second electrode layers. The method can further include attaching a device wafer to the coating, processing the device wafer, and applying a bias voltage to the first and second electrode layers. Applying the bias voltage can separate the device wafer from the carrier wafer.

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and one or more silicon carbide materials adjacent to the one or more stacks of materials. The materials of the one or more stacks comprise a single chalcogenide material and one or more of a conductive carbon material, a conductive material, and a hardmask material. The one or more silicon carbide materials comprises silicon carbide, silicon carboxide, silicon carbonitride, silicon carboxynitride, and also comprise silicon-carbon covalent bonds. The one or more silicon carbide materials is configured as a liner or as a seal. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

Abstract: Methods, systems, and devices for single etch and pier merge method for cell and comb features are described. One or more pillars and one or more piers for a memory array may be patterned, aligned, and formed in one processing step. For example, the one or more piers and the one or more pillars may be patterned and etched using a pillar shape to form a set of pillar cavities. A first subset of the pillar cavities may be etched such that pairs of adjacent pillar cavities merge to form a pier cavity that is filled with a first material and a liner to form the one or more piers. A second subset of the pillar cavities may be filled with the liner and the first material to form the one or more pillars. Comb edge structures may be formed based on a third subset of the pillar cavities.

Abstract: Techniques are described to form a liner to protect a material, such as a storage element material, from damage during subsequent operations or phases of a manufacturing process. The liner may be bonded to the material (e.g., a chalcogenide material) using a strong bond or a weak bond. In some cases, a sealant material may be deposited during an etching phase of the manufacturing process to prevent subsequent etching operations from damaging a material that has just been etched.

Abstract: Methods, systems, and devices for depositing carbon films using a single precursor are described. ALD may be performed by reacting a single precursor with a base material over multiple ALD cycles to thermally deposit a layer of carbon on the base material. For instance, each of the ALD cycles may include reacting a carbon-containing precursor with the base material in a chamber and performing a purge operation to remove contaminant materials (e.g., side products of the reaction, at least portions of the single precursor) from the chamber.

Abstract: Methods, systems, and devices for methods for selectively depositing carbon on substrates by atomic layer deposition are described. The described techniques include single precursor and multiple precursor atomic layer deposition processes. For instance, a device may react a first precursor with a first material and a second material to form a carbon compound on the first material and not the second material. The materials may be associated with different growth delays based on being exposed to the first precursor. Multiple precursors may be used where one or both of the precursors may have different growth delays for the first and second materials.

Abstract: A semiconductor die assembly is introduced in this disclosure. The semiconductor die assembly includes one or more semiconductor dies, a dielectric layer disposed under a bottom surface of the one or more semiconductor dies, and metal fragments or a metal layer disposed under the dielectric layer, wherein metal-OH bonds or metal-O—Si—OH bonds are disposed on a bottom surface of the dielectric layer. Alternatively, the semiconductor die assembly includes one or more semiconductor dies, a metal layer disposed under a bottom surface of the one or more semiconductor dies, and a metal oxidation layer disposed under the dielectric layer, wherein the metal oxidation layer comprises metal-OH bonds or metal-O—Si—OH bonds.

Abstract: A microelectronic device comprises conductive structures and insulative structures vertically alternating with the conductive structures. At least one of the insulative structures includes interfacial regions extending inward from vertical boundaries of the at least one of the insulative structures, and central region vertically interposed between the interfacial regions. The interfacial regions are doped with one or more of carbon and boron. The insulative structures comprise a lower concentration of the one or more of carbon and boron than the interfacial regions. Additional microelectronic devices, electronic systems, and methods are also described.

Abstract: Methods, systems, and devices for replacement channel integration for three dimensional memory cell architectures are described. A method of manufacturing a memory architecture may include forming a stack of materials above a substrate. Trenches may be formed within the stack of materials, where each trench may include a gate oxide material lining the trench, and pairs of conductive pillars forming gate elements. The gate elements may form word lines associated with activating memory cells of the memory architecture. Another trench may be formed perpendicular to the trenches, and used for forming memory cells each including a selection element and a storage element within sacrificial layers of the stack of materials between the trenches. The trench may form a source line for accessing the memory cells adjacent to the trench. A digit line may be formed around the trenches and may be configured to access the memory cells.

Abstract: Methods, systems, and devices for memory architectures with partially filled piers are described. A stack of materials including alternating layers of nitride and oxide may be formed, and piers and pillars may be formed through the stack of materials. Layers of nitride may be etched for metallization and one or more piers may be removed, which may result in corresponding cavities being formed in the stack of materials. Memory cells may be formed between one or more pillars and corresponding electrodes, and the cavities (e.g., the cavities resulting from removing one or more piers) may be partially filled with a dielectric material such that an air gap is formed within the cavity, or with a low-k dielectric material, or both.

Abstract: Methods, systems, and devices for a memory cell sealant material in a three-dimensional memory array are described. After forming a memory cell, a sealant material may be formed. The sealant material may include some material with a relatively high dielectric constant on the memory cell. The sealant material may be located between the memory cell and a pillar and may prevent or reduce diffusion between the memory cell and the pillar while supporting the memory cell being accessed. The sealant material may be formed as one or more layers of materials and may be associated with a relatively high dielectric constant, such that the sealant material may support low temperature deposition.

Abstract: A microelectronic device comprises conductive structures and insulative structures vertically alternating with the conductive structures. At least one of the insulative structures includes interfacial regions extending inward from vertical boundaries of the at least one of the insulative structures, and central region vertically interposed between the interfacial regions. The interfacial regions are doped with one or more of carbon and boron. The insulative structures comprise a lower concentration of the one or more of carbon and boron than the interfacial regions. Additional microelectronic devices, electronic systems, and methods are also described.

Abstract: Methods, systems, and devices for contact formation for a memory device are described. A memory device manufacturing operation may include forming bit lines and word lines in a same step. In some cases, the memory device may include word line contact portions that couple respective word lines with respective word line contacts located below the word lines. For example, the word line contact portions may be located between word lines and a substrate of the memory array. In such cases, the processing step may be used for formation of word lines, bit lines, and word line contact portions. Additionally, or alternatively, the memory device manufacturing operation may include forming a sacrificial ring around bit line contacts, which may isolate bit line contacts from a nitride layer.

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and one or more silicon carbide materials adjacent to the one or more stacks of materials. The materials of the one or more stacks comprise a single chalcogenide material and one or more of a conductive carbon material, a conductive material, and a hardmask material. The one or more silicon carbide materials comprises silicon carbide, silicon carboxide, silicon carbonitride, silicon carboxynitride, and also comprise silicon-carbon covalent bonds. The one or more silicon carbide materials is configured as a liner or as a seal. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

Abstract: Techniques are described to form a liner to protect a material, such as a storage element material, from damage during subsequent operations or phases of a manufacturing process. The liner may be bonded to the material (e.g., a chalcogenide material) using a strong bond or a weak bond. In some cases, a sealant material may be deposited during an etching phase of the manufacturing process to prevent subsequent etching operations from damaging a material that has just been etched.

Abstract: An electronic device comprising a stack structure comprising one or more stacks of materials and one or more silicon carbide materials adjacent to the one or more stacks of materials. The materials of the one or more stacks comprise a single chalcogenide material and one or more of a conductive carbon material, a conductive material, and a hardmask material. The one or more silicon carbide materials comprises silicon carbide, silicon carboxide, silicon carbonitride, silicon carboxynitride, and also comprise silicon-carbon covalent bonds. The one or more silicon carbide materials is configured as a liner or as a seal. Additional electronic devices are disclosed, as are related systems and methods of forming an electronic device.

Abstract: Methods, systems, and devices for a single plug flow for a memory device are described. In some examples, the memory device may include one or more plugs formed above respective bit line plates. The plugs may include a liner and one or more sacrificial materials that are removed during a subsequent etching operation. Accordingly, pillars may be formed above the plugs, and may be generally aligned with the respective bit line plates.

Abstract: Methods, systems, and devices for memory cell protective layers in a three-dimensional memory array are described. A memory device may support accessing memory cells of a memory array arranged in a three-dimensional architecture. The three-dimensional architecture may include levels of memory cells separated by levels of dielectric materials, such that the memory cells are formed between the dielectric materials. To prevent or reduce diffusion between a given memory cell and the dielectric materials, a barrier material may be formed on the dielectric material before forming the memory cell. The barrier material may be located between the memory cell and dielectric material, which may reduce or prevent material diffusion.

Abstract: Techniques are described to form a liner to protect a material, such as a storage element material, from damage during subsequent operations or phases of a manufacturing process. The liner may be bonded to the material (e.g., a chalcogenide material) using a strong bond or a weak bond. In some cases, a sealant material may be deposited during an etching phase of the manufacturing process to prevent subsequent etching operations from damaging a material that has just been etched.