Abstract: Apparatus and methods are provided for regulating the power consumption within a wireless communications mobile handset. A base station transmits an RF power output designating signal that indicates a desired level of the RF power output from the mobile handset. The mobile handset receives the RF power output designating signal, where it is used to set the level of the DC power supplied to the mobile handset. In this manner, the minimum amount of power necessary to maintain linear operation of the mobile handset is expended in the mobile handset. The DC power level is set by internally generating a control signal. The level of the control signal is dictated by the desired level of the RF power output as indicated by the received RF power output designating signal. The control signal is then applied to an RF amplifier circuit contained within the mobile handset to set the DC power level.

Abstract: The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between a digital device and a radio frequency device (wireless RF digital device), and the circuitry of a system including the packaged devices. Even more particularly, the present invention relates to a wireless radio frequency digital device functional pathway configuration for the interface between the wireless radio frequency digital device and a system in which the wireless radio frequency digital device is embedded.

Abstract: A wireless control and/or data acquisition system in an integrated circuit comprises a digital device and a wireless device, e.g., a radio frequency (RF) device, an infrared device (IrDA), etc. A micro-electro-mechanical (MEM) device may also be included in the integrated circuit package. The MEM may be used as a sensor, non-volatile memory, a filter, a frequency determining resonator, and/or a control device in combination with the digital device. The digital device and RF device may have independent power and signal connections for signal isolation between the digital device and RF device. Standby and sleep modes for the digital device and RF device reduce power consumption and low voltage operation enables the use of a simple battery power source.

Abstract: An apparatus for low power radio communication comprising a transmitter having a frequency synthesizer and transmit antenna such that the frequency synthesizer comprises a phase locked loop circuit with a voltage controlled oscillator having a variable frequency output and with a loop filter/sample and hold circuit that allows opening of the synthesizer control loop and with special means of limiting the resulting frequency drift in the open loop state. The transmitter produces an output signal and the loop filter/sample and hold circuit holds the voltage controlled oscillator substantially on frequency such that the output signal remains stable, with a minimum of frequency drift, over a period of time when the phase lock loop synthesizer is set to an open loop state to allow frequency modulation unimpeded by the normal frequency correcting action of the synthesizer and for the frequency synthesizer to be partially powered down to reduce power consumption.

Abstract: The present invention relates to a frequency modulated system, and a method for operating same, including a phase locked loop frequency synthesizer circuit which synthesizes a carrier frequency through the use of an electronically controlled oscillator. The circuit, which has a certain loop bandwidth, includes a reference frequency source and a bypassed correcting integrator. A modulating signal simultaneously modulates the oscillator, the reference frequency source and the bypassed correcting integrator such that the carrier frequency is frequency modulated with a certain frequency deviation. The magnitude of the modulation of the oscillator, the reference frequency source and the correcting integrator are controlled over a frequency range by frequency blending the reference frequency source and the bypassed correcting integrator such that low distortion modulation over a wide frequency range is achieved.

Abstract: An adaptable DC power consumption circuit is provided, wherein a controller alternately operates an RF amplifier during a high RF output power condition, and bypasses the RF amplifier during a low RF output power condition. In this manner, linear operation of the RF amplifier can be maintained while maximizing the power efficiency of the RF amplifier.

Abstract: An adaptable DC power consumption circuit is provided, wherein the voltage supplied to an RF amplifier is dynamically varied from a desired level. A feedback control loop is formed between the power terminal and a control terminal of a variable voltage supply. A controller influences the feedback control loop to properly set the supply voltage at the desired minimum level necessary to maintain linear operation of the RF amplifier. The output of the RF amplifier influences the feedback control loop to dynamically vary the supply voltage from the desired level. In this manner, linear operation of the RF amplifier can be maintained while maximizing the power efficiency of the RF amplifier.

Abstract: An adaptable DC power consumption circuit is provided, wherein the current supplied to an RF amplifier is dynamically varied from a desired level. A feedback control loop is formed between the power terminal and the control terminal of the RF amplifier. A controller influences the feedback control loop to properly set the supply current at the desired minimum level necessary to maintain linear operation of the RF amplifier. The output of the RF amplifier influences the feedback control loop to dynamically vary the supply current from the desired level. In this manner, linear operation of the RF amplifier can be maintained while maximizing the power efficiency of the RF amplifier.

Abstract: A receiver for efficient wireless communications in the presence of frequency errors in a radio frequency received signal is disclosed. The receiver comprising a receiver channel, a wide band frequency acquisition mode, automatic frequency control, a narrow band demodulation mode and a demodulator. The receiver channel has a variable bandwidth and an approximately fixed receiver mid-channel frequency. The wide band frequency acquisition mode comprises a wide channel filter which initially defines the bandwidth to be greater than the frequency error in the received signal and wherein the frequency error is determined by comparing the received signal frequency to the receiver mid-channel frequency.

Abstract: A frequency locked loop frequency synthesizer is comprised of a loop including a voltage controlled oscillator, a phase lock locked loop frequency detector, a divide by N counter and a low pass loop filter. A steering voltage is applied to the loop filter to produce a desired frequency or frequencies. The frequency lock loop frequency synthesizer drives the voltage controlled oscillator frequency to be N times the reference frequency. The frequency lock loop synthesizer inherently has 90 degrees less loop phase shift than a conventional phase lock loop. Additionally, the frequency lock loop frequency synthesizer provides a highly accurate, continuously tuneable, frequency synthesizer that includes a linear frequency detector in the frequency lock loop.