Abstract: An improved method and apparatus for connecting various function modules located within a computer or communications system are proposed. In accordance with the principles of the present invention, a port manager controller (PMC) has a direct interface to each of the function modules and to a host component such as a system memory or a CPU. The PMC replaces both the local bus and the arbitrator of prior art systems. All the requests by function modules to access the host component are first processed by the PMC. The PMC schedules the incoming requests in accordance with predefined parameters, such as priority, efficiency, and/or timing. The PMC is capable of handling more than one request at a time. The PMC is also capable of dynamically adapting to load conditions and rearranging the incoming requests to efficiently utilize the available bandwidth. Thus, the PMC reduces latency and improves the performance of the computer or communications system.

Abstract: A host device SCSI bus controller in SCSI bus system for uniformly distributing I/O tasks, thereby providing all devices equal access to a SCSI bus without decreasing the overall utilization of the bus. The controller prevents system errors from occurring due to I/O tasks not being transmitted when the connectivity of the bus is fully utilized and the bus is operating near saturation. The controller alters the host device performance during the arbitration phase by replacing the single occurrence of the SCSI standard specified arbitration phase with multiple arbitration phases. In the multiple arbitration phases the controller does not assert the host device ID until a user determined time after the completion of the SCSI standard specified arbitration phase.

Abstract: An I/O interface controller is disclosed which can be programmed to interact with a variety of interface protocols. The host side and the peripheral side of the interface controller are independently programmable. All significant operations are performed in a single chip gate array. The gate array includes registers for establishing control with peripheral devices and for transferring data between peripheral devices and the host. An arithmetic logic unit is used for calculation and data manipulation while an I/O operation is occurring. A condition code multiplexer evaluates the contents of registers within the single chip and instructs the sequencer to perform various operations based on these results. Strobe signals from a peripheral device, indicating that valid data is ready to be transferred, are quickly acknowledged by virtue of an asynchronous signal path. The strobe signal is also processed so that it may correspond with the internal clock of the I/O interface.

Abstract: A port adapter for an input/output system for a large data processing system. The port adapter is coupled to an I/O processor of that system and also to main memory of the system so that when the port adapter is selected by a system interrupt message from the I/O processor, it can begin and carry on its data transmission between a selected peripheral device and main memory without further assistance. The port adapter has two peripheral interface transceivers so that it can concurrently control data transfers to at least two peripheral devices.