Abstract: Various aspects include methods for implementing retaining high locality data in a higher level cache memory on a computing device. Various aspects may include receiving a cache access request for a first cache line in the higher level cache memory indicating a locality of the first cache line, determining whether the access request indicates high locality, and setting a high locality indicator of the first cache line in response to determining that the cache access request indicates high locality. Various aspects may include determining whether a lower level cache memory hit counter of a first cache line of a first cache exceeds a lower level cache locality threshold, setting a high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter exceeds the lower level cache locality threshold and resetting the lower level cache memory hit counter of the first cache.

Abstract: Various aspects include methods for implementing retaining high locality data in a higher level cache memory on a computing device. Various aspects may include receiving a cache access request for a first cache line in the higher level cache memory indicating a locality of the first cache line, determining whether the access request indicates high locality, and setting a high locality indicator of the first cache line in response to determining that the cache access request indicates high locality. Various aspects may include determining whether a lower level cache memory hit counter of a first cache line of a first cache exceeds a lower level cache locality threshold, setting a high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter exceeds the lower level cache locality threshold and resetting the lower level cache memory hit counter of the first cache.

Abstract: Aspects include computing devices and methods implemented by the computing for automatic cache coherency for page table data on a computing device. Some aspects may include modifying, by a first processing device, page table data stored in a first cache associated with the first processing device, receiving, at a page table coherency unit, a page table cache invalidate signal from the first processing device, issuing, by the page table coherency unit, a cache maintenance operation command to the first processing device, and writing, by the first processing device, the modified page table data stored in the first cache to a shared memory accessible by the first processing device and a second processing device associated with a second cache storing the page table data.

Abstract: Various aspects include methods for implementing retaining high locality data in a higher level cache memory on a computing device. Various aspects may include receiving a cache access request for a first cache line in the higher level cache memory indicating a locality of the first cache line, determining whether the access request indicates high locality, and setting a high locality indicator of the first cache line in response to determining that the cache access request indicates high locality. Various aspects may include determining whether a lower level cache memory hit counter of a first cache line of a first cache exceeds a lower level cache locality threshold, setting a high locality indicator of the first cache line in response to determining that the lower level cache memory hit counter exceeds the lower level cache locality threshold and resetting the lower level cache memory hit counter of the first cache.

Abstract: Various aspects include methods for implementing reducing clean evictions in an exclusive cache memory hierarchy on a computing device. Various aspects may include receiving a signal relating to a victim cache line candidate in a higher level cache memory that may include an accessed indicator of the victim cache line candidate or a demote message. A hit counter and/or an inclusion mode indicator of a victim cache line in a lower level cache memory that corresponds to the victim cache line candidate may be updated in response to receiving the signal. Updating the hit counter may depend on determining whether the accessed indicator is set, and may include increasing or decreasing the hit counter. Updating the inclusion mode indicator may depend on determining whether the accessed indicator is set and/or whether the hit counter exceeds an inclusion mode threshold, and may include setting or resetting the inclusion mode indicator.

Abstract: Various aspects include methods for implementing reuse aware cache line insertion and victim selection in large cache memory on a computing device. Various aspects may include receiving a cache access request for a cache line in a higher level cache memory, updating a cache line reuse counter datum configured to indicate a number of accesses to the cache line in the higher level cache memory during a reuse tracking period in response to receiving the cache access request, evicting the cache line from the higher level cache memory, determining a cache line locality classification for the evicted cache line based on the cache line reuse counter datum, inserting the evicted cache line into a last level cache memory, and updating a cache line locality classification datum for the inserted cache line.

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for input/output-coherent look-ahead cache access on a computing device.

Abstract: Aspects include computing devices and methods implemented by the computing for automatic cache coherency for page table data on a computing device. Some aspects may include modifying, by a first processing device, page table data stored in a first cache associated with the first processing device, receiving, at a page table coherency unit, a page table cache invalidate signal from the first processing device, issuing, by the page table coherency unit, a cache maintenance operation command to the first processing device, and writing, by the first processing device, the modified page table data stored in the first cache to a shared memory accessible by the first processing device and a second processing device associated with a second cache storing the page table data.