Abstract: Methods and systems for reducing delay in a comparator of an ADC are disclosed. In one embodiment, an ADC comprise a first analog-to-digital convertor stage. The ADC further comprises a second analog-to-digital convertor stage configured to receive the residue signal, output, a second digital value, and shift the residue signal by an amount based on a delay between the output of a digital value and a time of the first analog signal crossing an input reference signal. The ADC further comprises a combiner configured to receive the first digital value and the second digital value and combine the first digital value and the second digital value into an output representing a digital version of the first analog signal.

Abstract: The disclosed technology can be used to convert direct-current voltage and current from an input to a different or the same voltage and current at an output. One example direct-current to direct-current (DC-DC) power converter includes a first switch connected between a source voltage and a first side of an inductor, a second switch connected between the first side of the inductor and a ground, a third switch connected between a second side of the inductor and the ground, and a fourth switch connected between the second side of the inductor and a capacitor. The power converter may further include a comparator configured to compare an output voltage at the capacitor to a threshold voltage and based on the result of the comparison selectively activate or deactivate the first, second, third, and fourth switches in a power cycle.

Abstract: The disclosed technology can be used to convert direct-current voltage and current from an input to a different or the same voltage and current at an output. One example direct-current to direct-current (DC-DC) power converter includes a first switch connected between a source voltage and a first side of an inductor, a second switch connected between the first side of the inductor and a ground, a third switch connected between a second side of the inductor and the ground, and a fourth switch connected between the second side of the inductor and a capacitor. The power converter may further include a comparator configured to compare an output voltage at the capacitor to a threshold voltage and based on the result of the comparison selectively activate or deactivate the first, second, third, and fourth switches in a power cycle.

Abstract: A method for temperature mitigation includes receiving a signal from a temperature sensor that is disposed within a computing device. A processor chip within the computing device produces heat. The signal from the temperature sensor is converted to temperature data. The method further includes processing the temperature data to generate an estimate of a temperature of an external surface of the device. The processing includes applying a low pass filter to the temperature data, applying an amplitude attenuation to the temperature data, and applying a delay to the temperature data. The method further includes reducing an operating parameter of the processor chip, such as operating frequency, in response to the estimated temperature of the external surface of the device.

Abstract: An integrated circuit device, such as a system-on-a-chip (SOC) device that includes an integrated or embedded voltage regulator, comprises an integrated capacitor and an integrated inductor having a magnetic core that can be fabricated in the same process as the capacitive structure of the integrated capacitor.

Abstract: A semiconductor device may include a semiconductor die having an active region. The semiconductor device may also include a thermocouple mesh proximate to the active region. The thermocouple mesh may include a first set of wires of a first material extending in a first direction, and a second set of wires of a second material. The second material may be different from the first material. In addition, the second set of wires may extend in a second direction different than the first direction of the first wires.

Abstract: The disclosed technology can be used to convert direct-current voltage and current from an input to a different or the same voltage and current at an output. One example direct-current to direct-current (DC-DC) power converter includes a first switch connected between a source voltage and a first side of an inductor, a second switch connected between the first side of the inductor and a ground, a third switch connected between a second side of the inductor and the ground, and a fourth switch connected between the second side of the inductor and a capacitor. The power converter may further include a comparator configured to compare an output voltage at the capacitor to a threshold voltage and based on the result of the comparison selectively activate or deactivate the first, second, third, and fourth switches in a power cycle.

Abstract: Some novel features pertain to an inductor structure that includes a first inductor winding, a second inductor winding and a filler. The first inductor winding includes an electrically conductive material. The second inductor winding includes an electrically conductive material. The filler is laterally located between the first inductor winding and the second inductor winding. The filler is configured to provide structural coupling of the first and second inductor windings. In some implementations, the first inductor winding is laterally co-planar to the second inductor winding. In some implementations, the first inductor winding has a first spiral shape and the second inductor winding has a second spiral shape. In some implementations, the first inductor winding and the second inductor winding have an elongated circular shape. In some implementations, the filler is an epoxy.

Abstract: A semiconductor device may include a semiconductor die having an active region. The semiconductor device may also include a thermocouple mesh proximate to the active region. The thermocouple mesh may include a first set of wires of a first material extending in a first direction, and a second set of wires of a second material. The second material may be different from the first material. In addition, the second set of wires may extend in a second direction different than the first direction of the first wires.

Abstract: A circuit including: a three-level buck converter having: a plurality of input switches and an inductor configured to receive a voltage from the plurality of input switches, the plurality of input switches coupled with a first capacitor and configured to charge and discharge the first capacitor; a second capacitor at an output of the buck converter; and a switched capacitor at an input node of the inductor, wherein the switched capacitor is smaller than either the first capacitor or the second capacitor.

Abstract: A circuit including: a control system for a three-level buck converter, the three-level buck converter including multiple input switches, each of the input switches receiving one of a plurality of different pulse width modulated signals, the control system including: a first clock signal and a second clock signal, the second clock signal being a phase-shifted version of the first clock signal; ramp generating circuitry receiving the first and second clock signals and producing first and second ramp signals, respectively, from the first and second clock signals; a first comparing circuit receiving the first ramp signal and producing a first one of the pulse width modulated signals therefrom; and a second comparing circuit receiving the second ramp signal and producing a second one of the pulse width modulated signals therefrom.

Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply connects a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. Integration of the voltage regulator on the SoC reduces parasitic impedance be between the voltage regulator and the load to aid in reducing voltage droops. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.

Abstract: An apparatus and method are disclosed for providing efficient operation in a feedback loop having a synchronous buck converter. The synchronous buck converter includes a plurality of individually selectable phases, where each of the phases has a plurality of individually selectable and parallel switching legs. The circuit stores information that associates multiple different load values with respective configuration settings that each define a number of phases and a number of switching legs. As the load changes, the circuit measures the load and selects an appropriate configuration setting. The circuit applies the selected configuration setting to operate the number of phases and a number of parallel switching legs in the buck converter.

Abstract: An apparatus and method are disclosed for efficiently using power at a voltage regulator, such as a synchronous buck converter. The synchronous buck converter includes a first switch and a second switch operated by a first control signal and a second control signal, respectively, where the first and second control signals have a corresponding phase difference. A logic circuit measures a duty cycle of an input pulse width modulated (PWM) signal against iterative changes of the phase difference between the first control signal and the second control signal. The logic circuit selects a phase difference corresponding to a minimum value of the PWM signal, thereby optimizing dead time at the synchronous buck converter. The logic circuit may include a Digital Pulse Width Modulator.

Abstract: An apparatus and method are disclosed for providing voltage control at a load of a buck converter. The buck converter is in a feedback loop so that a reference voltage determines a pulse width modulated (PWM) signal that is fed to the buck converter, and an output voltage of the buck converter is fed back to a PWM control circuit to maintain a value of the output voltage. The load at the buck converter provides event counters to a transient load current prediction circuit, which uses a curve fitting algorithm or other adaptive control algorithm to predict a change in current at the load. The transient load current prediction circuit then manipulates the reference voltage in accordance with the predicted change in current at the load.

Abstract: A switch-mode power supply is provided that includes a comparator for producing a pulse-width modulated (PWM) controller clock signal for controlling a power switch in the switch-mode power supply. The switch-mode power supply is configured to superimpose a DC-free version of a ramp voltage with an error voltage to produce a combined voltage. The comparator compares the combined voltage to a reference voltage to produce the PWM controller clock signal.

Abstract: A method includes: receiving an electrical signal from a temperature sensor, wherein the temperature sensor is disposed within a package including a processor chip, further wherein the temperature sensor is thermally separated from the processor chip by materials within the package, generating temperature information from the electrical signal, processing the temperature information to determine that a performance of the processor chip should be mitigate, and mitigating the performance of the processor chip in response to the temperature information, wherein processing the temperature information and mitigating the performance of the processor are performed by the processor chip.

Abstract: A method for temperature mitigation includes receiving a signal from a temperature sensor that is disposed within a computing device. A processor chip within the computing device produces heat. The signal from the temperature sensor is converted to temperature data. The method further includes processing the temperature data to generate an estimate of a temperature of an external surface of the device. The processing includes applying a low pass filter to the temperature data, applying an amplitude attenuation to the temperature data, and applying a delay to the temperature data. The method further includes reducing an operating parameter of the processor chip, such as operating frequency, in response to the estimated temperature of the external surface of the device.

Abstract: An integrated circuit device, such as a system-on-a-chip (SOC) device that includes an integrated or embedded voltage regulator, comprises an integrated capacitor and an integrated inductor having a magnetic core that can be fabricated in the same process as the capacitive structure of the integrated capacitor.

Abstract: A method includes: generating a power consumption reading indicative of power consumption of a device, comparing the power consumption reading to a power threshold, wherein the power threshold represents a level of power consumption corresponding to a rise in temperature of an exterior surface of the device; in response to determining that the power consumption reading exceeds the power threshold, measuring cumulative power consumption over time from the power consumption reading; comparing the cumulative power consumption over time to an energy threshold, wherein the energy threshold corresponds to a temperature threshold for the exterior surface of the device; and in response to determining that the cumulative power consumption over time exceeds the energy threshold, reducing an operating parameter of the device to reduce power consumption.