Abstract: Techniques and systems for extending the capture range of frequency offset error detection are described. For instance, the present disclose describes efficient frequency estimation structures (e.g., zero crossing minimum/maximum (min/max) structures) that may extend carrier frequency offset error capture range by running a bank (e.g., a set) of parallel capture range structures trialing different frequency errors. In some aspects, a set of frequency offset estimation circuits and a set of correlation circuits (e.g., 1-bit correlators) may be used on parallel streams to perform correlation operations on each branch of a received bit stream to determine correlations with known preamble patterns (e.g., to accurately estimate large frequency offset errors).

Abstract: Techniques and systems for extending the capture range of frequency offset error detection are described. For instance, the present disclose describes efficient frequency estimation structures (e.g., zero crossing minimum/maximum (min/max) structures) that may extend carrier frequency offset error capture range by running a bank (e.g., a set) of parallel capture range structures trialing different frequency errors. In some aspects, a set of frequency offset estimation circuits and a set of correlation circuits (e.g., 1-bit correlators) may be used on parallel streams to perform correlation operations on each branch of a received bit stream to determine correlations with known preamble patterns (e.g., to accurately estimate large frequency offset errors).

Abstract: An apparatus and method for carrier frequency estimation include a carrier frequency estimator having: a frequency input terminal disposed to receive a frequency-domain input signal comprising a plurality of symbols; a plurality of candidate pipelines, each comprising a frequency adder coupled to the frequency input terminal, a bit converter coupled to the frequency adder, a multi-bit buffer coupled to the bit converter; and a correlator coupled to the multi-bit buffer, respectively; and a candidate pipeline selector coupled to the correlators.

Abstract: In certain aspects, a digital circuit comprises a delay line to generate a plurality of delayed versions of an input clock. The digital circuit also comprises selection circuitry to provide a selected one of the plurality of delayed versions of the input clock based on a clock selection signal and feedback circuitry to generate the clock selection signal based on the selected one of the plurality of delayed versions of the input clock and based on the input clock. The clock selection signal is further used for selecting and generating other clocks and/or for variation control.

Abstract: An apparatus and method for carrier frequency estimation include a carrier frequency estimator having: a frequency input terminal disposed to receive a frequency-domain input signal comprising a plurality of symbols; a plurality of candidate pipelines, each comprising a frequency adder coupled to the frequency input terminal, a bit converter coupled to the frequency adder, a multi-bit buffer coupled to the bit converter; and a correlator coupled to the multi-bit buffer, respectively; and a candidate pipeline selector coupled to the correlators.

Abstract: In certain aspects, a digital circuit comprises a delay line to generate a plurality of delayed versions of an input clock. The digital circuit also comprises selection circuitry to provide a selected one of the plurality of delayed versions of the input clock based on a clock selection signal and feedback circuitry to generate the clock selection signal based on the selected one of the plurality of delayed versions of the input clock and based on the input clock. The clock selection signal is further used for selecting and generating other clocks and/or for variation control.

Abstract: In certain aspects, a digital circuit comprises a delay line to generate a plurality of delayed versions of an input clock. The digital circuit also comprises selection circuitry to provide a selected one of the plurality of delayed versions of the input clock based on a clock selection signal and feedback circuitry to generate the clock selection signal based on the selected one of the plurality of delayed versions of the input clock and based on the input clock. The clock selection signal is further used for selecting and generating other clocks and/or for variation control.

Abstract: A method of adjusting the transmission time of a signal in a radio link, the method being performed by a transmitter configured to transmit the signal over the radio link to a receiver and comprising the steps of ascertaining an accuracy that the receiver assumes for the transmitter's clock, calculating an assumed drift of the transmitter's clock based on the assumed accuracy of that clock and the time since a previous correlation between the transmitter's clock and the receiver's clock; and transmitting the signal at a time dependent on the assumed drift.

Abstract: The present invention provides a locked loop circuit in which the input clock signal is delayed according to a saw-tooth signal in order to output a range of frequencies not necessarily equal to an integer multiple of the input clock signal. The absolute value of the delay (i.e. the difference between the maximum and minimum values of the saw-tooth delay) can be calibrated by detecting the value of the circuit phase detector at the wrap point of the saw-tooth.

Abstract: The present invention provides a locked loop circuit in which the input clock signal is delayed according to a saw-tooth signal in order to output a range of frequencies not necessarily equal to an integer multiple of the input clock signal. The absolute value of the delay (i.e. the difference between the maximum and minimum values of the saw-tooth delay) can be calibrated by detecting the value of the circuit phase detector at the wrap point of the saw-tooth.

Abstract: A method of adjusting the transmission time of a signal in a radio link, the method being performed by a transmitter configured to transmit the signal over the radio link to a receiver and comprising the steps of ascertaining an accuracy that the receiver assumes for the transmitter's clock, calculating an assumed drift of the transmitter's clock based on the assumed accuracy of that clock and the time since a previous correlation between the transmitter's clock and the receiver's clock; and transmitting the signal at a time dependent on the assumed drift.

Abstract: The present invention is directed to methods and systems for allocating bandwidth (or other shared resource) among multiple masters. According to an aspect of the present invention, an arbiter assigns a bucket to each CPU (or other device) where each bucket holds the credits for that CPU. Each bucket has a predetermined fill rate and a drain rate. Depending on the priority given to a particular CPU, the corresponding bucket will drain (or fill) at a particular rate. For example, CPUs with a higher priority will drain at a slower rate. For each clock tick (or other period of time) that a CPU is stalled, a number of credits is accrued. The bucket with the highest number of credits has priority and will be given access to the shared resource (e.g., DRAM, SDRAM, SRAM, EPROM, etc.).

Abstract: A method and system is provided for interleaving multiple cycles streams from clients seeking SDRAM access. More particularly, a master scoreboard register is established for enabling the interleaving of many clients SDRAM access requests into a single stream optimized for maximum packing density of the different streams, thereby reducing the overhead associated with each individual stream. In one embodiment, at least one Master Score Board Register (MSBR) is provided for storing the order of cycles to go out of a controller/processor and to the SDRAM. If there is a set bit in a particular location in the MSBR then it means that the cycle is occupied and already allocated and cannot be used for anything else. If the bit is not set then the cycle that bit represents a vacant slot is ready for use by a client. Upon receipt of an SDRAM request, an interleaving engine identifies the bit locations in the MSBR associated with the requested cycles.

Abstract: A method and system is provided for interleaving multiple cycles streams from clients seeking SDRAM access. More particularly, a master scoreboard register is established for enabling the interleaving of many clients SDRAM access requests into a single stream optimized for maximum packing density of the different streams, thereby reducing the overhead associated with each individual stream. In one embodiment, at least one Master Score Board Register (MSBR) is provided for storing the order of cycles to go out of a controller/processor and to the SDRAM. If there is a set bit in a particular location in the MSBR then it means that the cycle is occupied and already allocated and cannot be used for anything else. If the bit is not set then the cycle that bit represents a vacant slot ready for use by a client. Upon receipt of an SDRAM request, an interleaving engine identifies the bit locations in the MSBR associated with the requested cycles.

Abstract: A method and system is provided for generating pseudo-random numbers utilizing techniques of both the SHA-1 and DES encryption standards, wherein a pseudo-random number generator is re-keyed periodically using an external input of physical randomness. In accordance with one embodiment of the present invention, a current seed value Sj is loaded from a non-volatile storage. Next, values E, representative of environmental randomness, and C, representative of configuration data are likewise loaded. A new seed value, Sj+1, is generated in accordance with the equation Sj+1=f (Sj; A; C; E), wherein f represents a selected encryption algorithm, and B is a second constant, and wherein Sj is concatenated with A, which is concatenated with C which is concatenated with E. The new seed is then written to the non-volatile storage. Next, a key, K, is generated in accordance with the equation K=f (Sj; B; C; E), wherein B is a second constant.

Abstract: The present invention is directed to a technique for improving access latency of multiple bank DRAMs. According to an embodiment of the present invention, address lines may be swapped to improve DRAM access latency and performance. According to another embodiment of the present invention, SDRAM performance may be improved by increasing the likelihood that cycles may be interleaved thereby reducing the overhead associated with opening and closing banks. The aspects of the present invention may be applied to multiple bank DRAM, such as SDRAM, DDR devices and/or other shared resource, in accordance with the present invention.

Abstract: The present invention is directed to methods and systems for allocating bandwidth (or other shared resource) among multiple masters. According to an aspect of the present invention, an arbiter assigns a bucket to each CPU (or other device) where each bucket holds the credits for that CPU. Each bucket has a predetermined fill rate and a drain rate. Depending on the priority given to a particular CPU, the corresponding bucket will drain (or fill) at a particular rate. For example, CPUs with a higher priority will drain at a slower rate. For each clock tick (or other period of time) that a CPU is stalled, a number of credits is accrued. The bucket with the highest number of credits has priority and will be given access to the shared resource (e.g., DRAM, SDRAM, SRAM, EPROM, etc.).