Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.

Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.

Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.

Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.

Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.

Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.

Abstract: Systems and methods are provided for decoding low density parity check (LDPC) codes with different circulant sizes using common decoding circuitry. The systems and methods include receiving a plurality of codewords corresponding to an LDPC code and determining a circulant size associated with the plurality of received codewords. In response to determining the circulant size associated with the plurality of received codewords, the systems and methods partition processing resources of the common decoding circuitry into a plurality of cells based on the determined circulant size and processing the plurality of received codewords simultaneously using the plurality of cells.

Abstract: Systems and methods for decoding low density parity check (LDPC) codes are provided. An input message, representing a codeword encoded using a parity check matrix, is processed and data associated with each of the layers of the parity check matrix is computed. A first layer of the parity check matrix includes a first circulant configured to be updated using the data associated with a second layer of the parity check matrix. A second circulant in the first layer of the parity check matrix, configured to be updated using the data associated with the second layer of the parity check matrix, is identified. The first and second circulants are updated using the data associated with the first and second layers of the parity check matrix.

Abstract: This disclosure relates generally to data decoding, and more particularly to iterative decoders for data encoded with a low-density parity check (LDPC) encoder. LDPC decoders are disclosed that use reduced-complexity circular shifters that may be used to decode predefined or designed QC-LDPC codes. In addition, methods to design codes which may have particular LDPC code performance capabilities and which may operate with such decoders using reduced-complexity circular shifters are provided. The generation of quasi-cyclic low density parity check codes and the use of circular shifters by LDPC decoders, may be done in such a way as to provide increased computational efficiency, decreased routing congestion, easier timing closure, and improved application performance.

Abstract: Systems and methods for decoding low density parity check (LDPC) codes are provided. An input message, representing a codeword encoded using a parity check matrix, is processed and data associated with each of the layers of the parity check matrix is computed. A first layer of the parity check matrix includes a first circulant configured to be updated using the data associated with a second layer of the parity check matrix. A second circulant in the first layer of the parity check matrix, configured to be updated using the data associated with the second layer of the parity check matrix, is identified. The first and second circulants are updated using the data associated with the first and second layers of the parity check matrix.

Abstract: This disclosure relates generally to data decoding, and more particularly to iterative decoders for data encoded with a low-density parity check (LDPC) encoder. LDPC decoders are disclosed that use reduced-complexity circular shifters that may be used to decode predefined or designed QC-LDPC codes. In addition, methods to design codes which may have particular LDPC code performance capabilities and which may operate with such decoders using reduced-complexity circular shifters are provided. The generation of quasi-cyclic low density parity check codes and the use of circular shifters by LDPC decoders, may be done in such a way as to provide increased computational efficiency, decreased routing congestion, easier timing closure, and improved application performance.

Abstract: Low-latency programmable encoders, and more particularly, low-latency programmable encoders which use low-density parity check (LDPC) codes in combination with an outer systematic code. The LDPC encoder is programmable for any irregular circulant-based LDPC code. The code profile, block length, number of block rows, and number of block columns can vary. The LDPC encoding and the outer systematic code encoding can proceed in a parallel manner (e.g., simultaneously) instead of in a serial manner.

Abstract: Low-latency programmable encoders, and more particularly, low-latency programmable encoders which use low-density parity check (LDPC) codes in combination with an outer systematic code. The LDPC encoder is programmable for any irregular circulant-based LDPC code. The code profile, block length, number of block rows, and number of block columns can vary. The LDPC encoding and the outer systematic code encoding can proceed in a parallel manner (e.g., simultaneously) instead of in a serial manner.

Abstract: A decoder rescales state metric values to avoid overflow by resetting a bit in state metric registers that store the state metric values for each state. For example, the decoder may monitor a most significant bit (MSB) of the state metric registers to determine when the state metric values for all of the states exceed a threshold value. Upon exceeding the threshold value, the decoder may rescale the state metric values to avoid overflow. For instance, when the state metric values exceed the threshold value, the MSBs of the state metric registers may be reset. Resetting the MSBs is equivalent to subtracting half of the maximum value of the state metric register. The resealing technique can prevent state metric value overflow while offering reduced complexity and reduced latency.