Abstract: An integrated hardware and software system detects and prevents accidental secure erase on a storage device. It includes a detection engine using a unique identifier on the storage device to identify if the information stored on the storage unit has been previously copied before allowing performance of secure erase on such storage device. When it is detected that the data has not been copied and verified, the system automatically blocks the secure erase function if enabled in the software application component. The system keeps track of the storage device history to be aware that the last function on the storage device, based on its unique identifier, was a secure erase so that the next time it detects data on the storage device, it is aware that this data is new data; not copied and checksum verified while triggering the disabling of the secure erase software component functionality.

Abstract: A dual connection peripheral device has a housing. A captive input/output cable is disposed at least partially within the housing and selectively connects the dual connection peripheral device to a host device. An auxiliary input/output port is disposed on the housing and selectively connects to the host. A control circuit is operatively coupled to the captive input/output cable and auxiliary input/output port and selectively connects one of the captive input/output cable and the auxiliary input/output port to the host device.

Abstract: Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.

Abstract: Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.

Abstract: Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.

Abstract: Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.