Abstract: Disclosed is a system and method for improving efficiency and overall capacity of data transmission within a given bandwidth in a GPRS/EDGE wireless air-link channel. A GPRS data terminal, mobile unit and/or other end-user equipment is equipped with a (specially designed) Trellis coder that replaces the traditional cyclic coder and allows encoding and decoding of data via the Trellis code algorithm. Trellis coder eliminates errors in data transmission, increases capacity in a given bandwidth, and corrects problems with fading channels associated with wireless transmission. The Trellis coder is also utilized for voice transmission and may be fabricated on an integrated circuit for utilization within hand-held devices.

Abstract: A plurality of terminals, such as digital telephones, are connected to a serial data bus formed by a balanced two-wire line. Each terminal transmits bytes bit-serially with the magnitude bits first, in order of decreasing significance, then the sign bit, and finally an even parity bit to maintain the balance of the line, the "1" bits being transmitted with alternating polarity. The terminals operate simultaneously and in synchronism. If a terminal, during a "0" bit of a byte which it is transmitting, detects a "1" pulse on the bus from another terminal, then it gives up transmission for the remainder of that byte and receives the greater magnitude byte which prevails on the bus. Thus a single two-wire line can be used for digital transmission in both directions between arbitrary numbers of telephones.

Abstract: A bit oriented protocol (e.g. HDLC) data link control multiplexer and demultiplexer are described for handling 256 channels whose data are time division multiplexed in pairs of bits in a serial data stream. The multiplexer and demultiplexer relieve a processor of an associated telephone or packet data switching office from the tasks of multiplexing and demultiplexing, formatting data link control frames, providing CRC checks, and inserting and removing zero bits to distinguish messages from flag bytes. The multiplexer and demultiplexer each include several shift registers for the serial bit stream information, byte boundary indication, CRC data, and effecting zero bit insertion and removal.

Abstract: A bit oriented protocol (e.g. HDLC) data link control multiplexer and demultiplexer are described for handling 256 channels whose data are time division multiplexed in pairs of bits in a serial data stream. The multiplexer and demultiplexer relieve a processor of an associated telephone or packet data switching office from the tasks of multiplexing and demultiplexing, formatting data link control frames, providing CRC checks, and inserting and removing zero bits to distinguish messages from flag bytes. The multiplexer and demultiplexer each include several shift registers for the serial bit stream information, byte boundary indication, CRC data, and effecting zero bit insertion and removal.

Abstract: Each of two terminals transmits a bit stream to a two-wire line in the form of a unipolar pulsed signal, the terminals transmitting pulses of opposite polarity with the bits synchronized, so that the line acts as a distributed exclusive-or gate. In each terminal, pulses on the bus are detected and a consequent received bit stream is exclusively-ored with the bit stream transmitted by this terminal to recover the bit stream transmitted by the other terminal.