Abstract: A trimmable and switchable current mirror can be used in a bandgap voltage reference to calibrate the voltage reference without requiring access to measurement of the quiescent current IQ of the voltage reference. Trimmable transistors within the current mirror are alternately selectable as the diode-connected transistor via a mirror switch signal. A bandgap voltage difference is computed for two bandgap voltage values measured for alternate switched configurations of the current mirror. A set of such differences is computed and stored for different trim configurations of the mirror transistors, and the trim configuration corresponding to the lowest absolute value bandgap voltage difference can be selected as the optimal trim configuration. Following mirror transistor trim adjustment, a bandgap resistor trim can be adjusted to further calibrate the bandgap voltage reference.

Abstract: A trimmable and switchable current mirror can be used in a bandgap voltage reference to calibrate the voltage reference without requiring access to measurement of the quiescent current IQ of the voltage reference. Trimmable transistors within the current mirror are alternately selectable as the diode-connected transistor via a mirror switch signal. A bandgap voltage difference is computed for two bandgap voltage values measured for alternate switched configurations of the current mirror. A set of such differences is computed and stored for different trim configurations of the mirror transistors, and the trim configuration corresponding to the lowest absolute value bandgap voltage difference can be selected as the optimal trim configuration. Following mirror transistor trim adjustment, a bandgap resistor trim can be adjusted to further calibrate the bandgap voltage reference.

Abstract: An integrated circuit includes an enable circuit and a main circuit. The enable circuit is configured to receive a supply voltage and an enable signal at a first voltage level, generate a start voltage by clamping the supply voltage to a threshold voltage level that is less than the supply voltage and generate an enable intermediate signal at a second voltage level that is less than the first voltage level and limited by the start voltage. In response to the enable intermediate signal being generated at the second voltage level, the enable circuit is configured to generate a start signal (such as a current). In response to the start signal being generated, the enable circuit is configured to generate an output signal at a third voltage level that is less than the first voltage level. The main circuit is configured to utilize the output signal as a supply voltage rail.

Abstract: An integrated circuit includes an enable circuit and a main circuit. The enable circuit is configured to receive a supply voltage and an enable signal at a first voltage level, generate a start voltage by clamping the supply voltage to a threshold voltage level that is less than the supply voltage and generate an enable intermediate signal at a second voltage level that is less than the first voltage level and limited by the start voltage. In response to the enable intermediate signal being generated at the second voltage level, the enable circuit is configured to generate a start signal (such as a current). In response to the start signal being generated, the enable circuit is configured to generate an output signal at a third voltage level that is less than the first voltage level. The main circuit is configured to utilize the output signal as a supply voltage rail.

Abstract: A power supply circuit, suitable for use in an integrated circuit, the circuit configured to detect whether an output voltage has been specified using an external resistance network. The power supply circuit is configured to determine the appropriate output voltage to be generated based on a voltage measured at a single input pin of the power supply circuit, where the single input pin provides a feedback voltage used in the control loop of the power supply circuit. Based on the feedback voltage at the input pin, the power supply circuit is configured to detect the presence of a resistance network external to the single input pin. If an external resistance network is detected, the power supply is configured to generate the output voltage specified at the input pin. If no external resistance network is detected, the power supply is configured to generate a default output voltage.

Abstract: Circuitry and method for providing a signal indicative of instances of conduction of average inductor current in a DC-to-DC voltage converter. Such signal identifies a time when the instantaneous average current being conducted by the inductor in a DC-to-DC voltage converter can be measured by providing a signal edge approximately halfway through one of the increasing and decreasing current conduction intervals of the inductor.

Abstract: Circuitry and method for providing a signal indicative of instances of conduction of average inductor current in a DC-to-DC voltage converter. Such signal identifies a time when the instantaneous average current being conducted by the inductor in a DC-to-DC voltage converter can be measured by providing a signal edge approximately halfway through one of the increasing and decreasing current conduction intervals of the inductor.

Abstract: A synchronous switching voltage regulator circuit is provided. After the first PWM pulse or at the end of a soft-start, a gradual transition is made from asynchronous rectification to fully synchronous rectification. The gradual transition to synchronous rectification is made by gradually increasing the time that the synchronous switch is enabled to be on.

Abstract: A synchronous switching voltage regulator circuit is provided. After the first PWM pulse or at the end of a soft-start, a gradual transition is made from asynchronous rectification to fully synchronous rectification, or vice versa. During the gradual transition, the error voltage is level-shifted down to correct for error caused by reverse current through the body diode of the main switch.

Abstract: An integrated circuit includes an oscillator circuit, where a frequency of an oscillator output signal provided by the oscillator circuit is adjustable by either coupling a resistor to an input pin, or by applying an external clock signal to the input pin. The oscillator circuit includes a comparator, a follower, a current-controlled oscillator, and a switch circuit. The switch circuit is coupled between the input pin and a node that is coupled to the current-controlled oscillator. Also, the follower is arranged to cause the voltage at the node to be at a pre-defined voltage unless the voltage at the node is overdriven by an external clock signal. The comparator circuit is arranged to determine whether the signal at the input pin is a clock signal. If it is determined that the signal at the input pin is a clock signal, the switch circuit is opened.

Abstract: A synchronous switching voltage regulator circuit is provided. After the first PWM pulse or at the end of a soft-start, a gradual transition is made from asynchronous rectification to fully synchronous rectification. The gradual transition to synchronous rectification is made by gradually increasing the time that the synchronous switch is enabled to be on.

Abstract: Devices, circuits, and methods generate a substantially constant output voltage. A power storage element generates a DC output voltage from an input voltage. The output is sampled to generate a feedback signal. An error amplifier generates an error signal from the feedback signal and a reference voltage. A ramp generator generates a ramp signal from the error signal. A comparator generates a pulse signal by comparing the ramp signal to a threshold voltage. The pulse signal is used to control a power switch, which switches the power storage element on and off. The pulse signal is generated such that, if the input voltage changes within a certain range, a width of its pulses changes so as to maintain the output voltage substantially constant.