Abstract: A system and method is disclosed for establishing a mirror configuration in a storage network. The storage network includes two storage drives that are coupled to one another according to a Serial Attached SCSI storage network interface. The storage drives determine whether the storage drives are coupled to one another. If it is determined that the storage drives are coupled to one another, the storage drives are configured in a mirror configuration in which write commands received at one of the drives are mirrored to the other drive.

Abstract: A system and method is disclosed for establishing a mirror configuration in a storage network. The storage network includes two storage drives that are coupled to one another according to a Serial Attached SCSI storage network interface. The storage drives determine whether the storage drives are coupled to one another. If it is determined that the storage drives are coupled to one another, the storage drives are configured in a mirror configuration in which write commands received at one of the drives are mirrored to the other drive.

Abstract: An SAS domain map is automatically generated at an SAS concentrator switch by a virtual mapping device that presents itself as a target for discovery by SAS devices interfaced with the concentrator, such as information handling systems and storage devices. During the SAS protocol discovery process, the virtual mapping device generates the SAS domain map by acquiring the device name and the device port for each concentrator port that interfaces with a device. A management application running on the concentrator applies the SAS domain map to provide network functions, such as zoning or diagnostics.

Abstract: A system and method for receiving and responding to issued commands in a storage enclosure is disclosed in which each storage enclosure processor of the storage enclosure is coupled to each expander of the storage enclosure. Each storage enclosure processor receives each interrupt and command issued by another expander of the storage enclosure. In the event of a failure of one of the storage enclosure processors, any interrupts or commands issued by the expander associated with the failed storage enclosure processor will be handled by the operational storage enclosure processor. In this configuration, the storage enclosure processor can also arbitrate or determine the storage enclosure processor that will handle each interrupt and any associated command.

Abstract: An architecture and a method for the automated configuration of a storage enclosure are disclosed. The disclosed storage enclosure includes an internal communications link between the storage controllers of the storage enclosure. The storage enclosure is operable to determine if the storage enclosure is a terminal storage enclosure or if the expansion ports of the storage enclosure are externally cabled. If the storage enclosure is the terminal storage enclosure, the internal communications link is enabled, providing a communications pathway between the two controllers that is internal to the storage enclosure.

Abstract: A network and a method for network operation are disclosed that facilitates the identification of a failure in the storage subsystem of the network and the recovery from such a failure. The storage subsystem includes storage enclosures that are coupled to each of the server nodes of the network. When a server node determines that it can no longer access a drive of the storage enclosure, the server node notifies the alternate server node of the network, which attempts to access the drive. If the alternate server node of the network can access the drive, the ownership of the logical unit that includes the drive is transferred to the alternate server node.

Abstract: An integrated cable tester detects cable faults by coupling a single cable to host and expander connectors of an interface module and determining whether each of plural ports of the connectors has an associated PHY Ready signal. An LED interfaced with the cable tester illuminates to indicate a normal cable and fails to illuminate if the cable tests faulty. In one embodiment a module tester determines whether the module has degraded performance when a single cable is detected as coupled to the host and expander connectors of the module. The module tester clears the interface module's error log and initiates a reset of communication between the host and expander ports. Upon completion of the reset, such as detection of all PHY Ready signals for the plural ports, the module tester reads the error log and indicates errors as degrading the performance of the interface module.

Abstract: A system and method is disclosed for identifying the storage drives of a computer network. An identifier associated with an element of the storage network is stored in nonvolatile memory and later retrieved. The identifier associates the elements of the storage network, allowing the storage drives of the storage enclosure to be associated with the storage enclosure itself.

Abstract: A configurable hardware for coupling to one of a plurality of hardware. Each of the plurality of hardware has a type. The configurable hardware includes a memory for storing an ID. The ID identifies the type of the hardware coupled to the configurable hardware.

Abstract: An I/O bridge system comprises a motherboard including first and second busses, e.g., first and second PCI busses. A I/O bridge circuit is connected between the first and second busses and operative to communicate therebetween. A first connector is disposed on a side of the motherboard and has the first bus provided thereat. A second connector is disposed on the side of the motherboard, positioned laterally adjacent the first connector and has the second bus provided thereat. An interconnected stack of daughterboards is disposed on the motherboard and connected to the first and second connectors of the motherboard. A daughterboard of the interconnected stack includes an I/O bridge circuit connected to one of the first bus or the second bus depending on the position of the daughterboard in the interconnected stack. The I/O bridge circuit is operative to communicate between one of the motherboard busses and a communications channel such as a Fibre Channel.

Abstract: An expandable bus system comprises a first bus and a second bus. A bus bridge detection circuit is operative to detect presence and absence of a common bridge circuit connected between the first bus and the second bus. A bus switching circuit is connected to the first bus and to the second bus, is responsive to the bus bridge circuit detection circuit and is operative to allow signal flow between the first bus and the second bus in response to detection of the absence of a common bus bridge circuit connecting the first bus and the second bus and to impede signal flow between the first bus and the second bus in response to detection of the presence of a common bus bridge circuit connecting the first bus and the second bus. In an embodiment, the first bus and the second bus are provided in a connector configured to releasably connect to a bus bridge circuit, and the bus bridge detection circuit is operative to detect presence and absence of a bus bridge circuit at the connector.

Abstract: First and second bus bridges, e.g., first and second RAID disk controllers, are operative to communicate between a first bus and a second bus via respective first and second caches and to transfer information from the first bus bridge to the second cache over a third bus, e.g., a synchronous data link between the caches, to allow recovery of data previously cached in the first cache via the second bus bridge. The second bus bridge preferably is operative to transfer information addressed to the first bus from the first bus to the second bus, e.g., to “alias” addresses normally assigned to the first bus bridge in event of a failure, disconnection or other change in status of the first bus bridge. The status may be communicated from the first bus bridge to the second bus bridge over a fourth bus connecting the first and second bus bridges.

Abstract: A redundant bus bridge system includes first and second bus bridges operative to transfer data between a first bus and a second bus, the first and second bus bridges being configured to receive power from respective separate power supplies. In one embodiment, the first bus bridge and the second bus bridge share a common ground reference. The first bus bridge may be included in a first circuit assembly configured to receive power at a power supply voltage. The second bus bridge may be included in a second circuit assembly including a input circuit having a maximum input voltage associated therewith. The first circuit assembly may be operative to apply an output signal to the input circuit of the second circuit assembly, the output signal having a voltage which varies with the power supply voltage but does not exceed the maximum input voltage.

Abstract: A redundant bus bridge system for communicating between a first bus and a second bus includes a first clock generator operative to produce a first clock signal and a second clock generator operative to produce a second clock signal. A first bus bridge, e.g., a first RAID controller, connects the first bus and the second bus and is responsive to the first clock generator and the second clock generator. The first bus bridge is operative to transfer data between the first bus and the second bus in synchronism with a selected one of the first clock signal and the second clock signal. A second bus bridge, e.g., a second RAID controller, connects the first bus and the second bus and is responsive to the first clock generator and the second clock generator. The second bus bridge is operative to transfer data between the first bus and the second bus in synchronism with a selected one of the first clock signal and the second clock signal.

Abstract: A power supply line of a communications interface provides communication between two devices when one device is unable to utilize the communications interface in a standard manner. The power supply line is specified to operate within a first voltage range and normally operates at a first voltage within a second voltage range, the second voltage range being within the first voltage range. A voltage circuit changes the power supply line to a second voltage outside of the second voltage range but within the first voltage range. A voltage detecting circuit coupled to the power supply line asserts a signal indicating when the second voltage is present on the power supply line, thereby providing communication between the first device and the other device.

Abstract: A self-shutdown system for a circuit card when removed from the connector of a primary system, where the circuit card includes a local power source for providing power when primary power is not available. A dedicated sense pin on the connector of the card is grounded to the remaining ground pins when the card is plugged in but floats or is otherwise disconnected when the card is unplugged from the primary system. A ground switch circuit connected to the sense pin and the remaining ground pins asserts a shutdown signal for disabling the circuitry on the card when the ground sense pin is floating or deasserts the shutdown signal when the ground sense pin is grounded. In one embodiment, the disable mechanism is a switch circuit for disconnecting the main circuitry of the card from the local power source. In the preferred embodiment, however, a DC/DC converter receives the shutdown signal and disables the remaining circuitry when the shutdown signal is asserted.

Abstract: A communication system for allowing a master to send commands to one or more slave devices across a normally static digital signal line of a bus. The master includes command logic for asserting a sequence of digital pulses according to a predetermined protocol with inherent timing to clock each data bit into a slave device. The master transmits several data bits to form each command, where each data bit is combined with clocking pulses to implement the self-clocking scheme. In particular, an initial data pulse incorporates a data bit to initiate a data phase. Each slave device includes a state machine which detects the data pulse and enables a sample and hold or latch circuit to capture the data bit. Then a clock pulse followed by a reset pulse is sent to clock the data into the slave device and reset the state machine. The slave also includes shift register logic to hold a command bit and address bits for each command.

Abstract: A fault tolerant isolation system providing fault tolerant electrical isolation between different components receiving power from separate power sources regardless of which of the power sources fails. One power source provides operating voltage to an isolation device, which is a transceiver, buffer, quick switch, etc. The other power source activates a transistor switch coupled to the output enable input of the isolation device, and a current limit device is provided between the output enable and power inputs of the isolation device. In this manner, failure of either power source disables the isolation device and therefore provides fault tolerant isolation between the devices on either side. In the preferred embodiment, the isolation device acts as a high impedance open switch if its power is removed thereby isolating the devices on either side.

Abstract: A battery charger including a control system for controlling a linear pass element to maintain relatively constant power dissipation of the linear pass element. In one embodiment, the charge current and the voltage across the linear pass element are provided to a constant dissipation amplifier, which increases the charge current as the voltage of the linear pass element decreases due to charging of the battery. The charge current is increased in such a manner to maintain the power dissipation of the linear pass element to a relatively constant level. In another embodiment, the battery voltage is provided to the amplifier, which increases charge current in response to rising battery voltage to maintain constant power dissipation of the linear pass element. The latter embodiment is in recognition that the voltage across the linear pass element is inversely proportional to the voltage across the linear pass element.