Abstract: In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to a supply via a second sleep transistor, and a virtual supply node between the second circuit block and the second sleep transistor. The circuit also includes a transmission gate (TG) or a pass transistor connecting the virtual ground node to the virtual supply node to enable charge recycling between the first circuit block and the second circuit block during transitions by the circuit between active mode and sleep mode.

Abstract: A method of forming a memory cell includes coupling a first transistor between a supply rail of a memory cell and a node operable to accept a supply voltage. The method further includes coupling a second transistor between a ground rail of the cell and a node operable to accept a ground. In one embodiment, the method includes forming the cell to accept selectively applied external voltages, wherein the external voltages are selected to minimize leakage current in the cell. In another embodiment, the method includes forming at least one of the first and the second transistors to have a channel width and/or a threshold voltage selected to minimize a total leakage current in the cell.

Abstract: In one embodiment, a method for power mode transition in a multi-threshold complementary metal oxide semiconductor (MTCMOS) circuit includes clustering logic cells in the circuit to a number of logic clusters and optimizing wake-up times of the logic clusters to reduce a total turn-on time of the circuit while keeping below a predetermined threshold a sum of currents flowing from the circuit to ground, a sum of currents flowing from a supply voltage to the circuit, or both during a transition by the circuit from sleep mode to active mode.

Abstract: A method and apparatus for generating processor test programs using a formal description of the processor's instruction set. An instruction set for a processor is formally described using a language such as ISDL. The formal description of the instruction set identifies certain characteristics of the instructions making up the instruction set. The formal description is combined with a test specification that describes desired properties of a test program by formally specifying test sequences that are to be applied to instructions having particular characteristics. A test program is generated by applying the formal test specification to the formal description of the instruction set including test sequences applicable to instructions having the particular characteristics.

Abstract: In one embodiment, a method for improving performance of a processor having a defective cache includes accessing first object code and generating second object code from the first object code. The generation of the second object code takes into account one or more locations of one or more defects in a cache on a processor such that one or more instructions in the second object code are written only to nondefective locations in the cache.

Abstract: In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to a supply via a second sleep transistor, and a virtual supply node between the second circuit block and the second sleep transistor. The circuit also includes a transmission gate (TG) or a pass transistor connecting the virtual ground node to the virtual supply node to enable charge recycling between the first circuit block and the second circuit block during transitions by the circuit between active mode and sleep mode.

Abstract: Techniques are provided for characterizing processor designs and estimating power consumption of software programs executing on processors. A power model of a processor may be obtained by performing simulation using one or more training programs to obtain average power consumption during one or more windows of operation, then using the results to select parameters and coefficients for a processor characterization equation that can estimate power consumption while minimizing error.

Abstract: In one embodiment, a memory block includes one or more bit lines that each include two or more cells. Each cell in each bit line has a distance from a sense amplifier coupled to the bit line, and each of one or more of the cells in each of one or more of the bit lines has a delay particularly set according to the distance of the cell from the sense amplifier coupled to the bit line.

Abstract: A method for reducing operations in a processing environment is provided that includes generating one or more binary representations. One or more of the binary representations are included in one or more linear equations that include one or more operations. The method also includes converting one or more of the linear equations to one or more polynomials and identifying one or more common subexpressions associated with the polynomials in order to reduce one or more of the operations. The identifying step is facilitated by an algorithm that iteratively selects divisors and then uses the divisors to eliminate common subexpressions among the linear equations. The method can also take into account the delay of expressions while performing the optimization. Further, it can optimize a polynomial to reduce the number of operations. Additionally, it can optimize the exponents of variables.

Abstract: A method for reducing transitions on a bus is provided that includes receiving an input trace and constructing a Markov source correlating to the input trace. The method also includes identifying an encoding technique, which can either minimize or maximize an objective function associated with the input trace.

Abstract: A method for event-driven observability enhanced coverage analysis of a program parses a program into variables and data dependencies, wherein the data dependencies comprise assignments and operations. The method builds a data structure having multiple records, with each record having at least one data dependency, a parent node, and a child node. Each node is linked to a variable. The method computes the value of each variable using the data structure. The method performs tag propagation based, at least in part, on the data dependencies and computed values.

Abstract: In one embodiment, a method for reducing power consumption at a cache includes determining a code placement according to which code is writable to a memory separate from a cache. The code placement reduces occurrences of inter cache-line sequential flows when the code is loaded from the memory to the cache. The method also includes compiling the code according to the code placement and writing the code to the memory for subsequent loading from the memory to the cache according to the code placement to reduce power consumption at the cache. In another embodiment, the method also includes determining a nonuniform architecture for the cache providing an optimum number of cache ways for each cache set in the cache. The nonuniform architecture allows cache sets in the cache to have associativity values that differ from each other. The method also includes implementing the nonuniform architecture in the cache to further reduce power consumption at the cache.

Abstract: In one embodiment, a method for reducing power consumption at a cache includes determining a nonuniform architecture for a cache providing an optimum number of cache ways for each cache set in the cache. The nonuniform architecture allows cache sets in the cache to have associativity values that differ from each other. The method also includes implementing the nonuniform architecture in the cache to reduce power consumption at the cache. In another embodiment, the method also includes determining a code placement according to which code is writeable to a memory separate from the cache. The code placement reduces occurrences of inter cache-line sequential flows when the code is loaded from the memory to the cache. The method also includes compiling the code according to the code placement and writing the code to the memory for subsequent loading from the memory to the cache according to the code placement to further reduce power consumption at the cache.

Abstract: A method for reducing operations in a processing environment is provided that includes generating one or more binary representations, one or more of the binary representations being included in one or more linear equations that include one or more operations. The method also includes converting one or more of the linear equations to one or more polynomials and then performing kernel extraction and optimization on one or more of the polynomials. One or more common subexpressions associated with the polynomials are identified in order to reduce one or more of the operations.

Abstract: An apparatus is provided that a way memoization, which may utilize a memory address buffer element that is operable to store information associated with previously accessed addresses. The memory address buffer element may be accessed in order to reduce power consumption in accessing a cache memory. A plurality of entries associated with a plurality of data segments may be stored in the memory address buffer element. For a selected one or more of the entries there is an address field that points to a way that includes a requested data segment. The memory address buffer element includes one or more ways that are operable to store one or more of the data segments that may be retrieved from the cache memory. One or more of the previously accessed addresses may be replaced with one or more tags and one or more set indices that correlate to the previously accessed addresses.

Abstract: A method for optimizing polynomial expressions is provided that includes generating kernels in order to form a kernel and co-kernel matrix and generating a cube literal matrix, which includes a plurality of cubes. Rectangles are identified on the kernel and co-kernel matrix and the rectangles are used to find common factors between the kernels. The rectangles on the cube literal matrix are identified and the rectangles are used to find common factors between the cubes.

Abstract: A method for reducing transitions on a bus is provided that includes receiving an input trace and constructing a Markov source correlating to the input trace. The method also includes identifying an encoding technique, which can either minimize or maximize an objective function associated with the input trace.

Abstract: An instruction-set-aware method for reducing transitions on an irredundant address bus comprises receiving a first address for communication to a memory on an irredundant address bus. The method retrieves an instruction from a memory location indicated by the first address, transmits the instruction on a data bus, and determines a category of the instruction. The method predicts a second address based, at least in part, on the first address, the instruction, and the category of the instruction.

Abstract: A processing system provides for analysis of sequential systems using binary time-frame expansion of these systems. This expansion technique produces models in which inputs and values for time may be treated as variables for producing various outputs and states.

Abstract: An encoder and decoder provide coding of information communicated on buses. The encoder and decoder may use various combinations of techniques to reduce switching activity on an address bus.