Abstract: A system and method of analyzing a powered device (PD) in a Power-over-Ethernet (PoE) system are presented. The system includes an Ethernet interface having a physical layer (PRY) chip capable of providing a signal pulse in addition to physical layer 1 functions. The system further includes a pulse transformer, coupled to the PRY chip, capable of relaying the signal pulse provided by the PRY chip to the PD via the transmit line and a second PRY chip. The first PRY chip receives one or more return pulse signals from the PD, analyzes characteristics such as voltage and/or frequency of the return pulse signal(s), and determines attributes of the PD based on those characteristics. The attributes can include powered device validity and power classification. A method of supplying power to a PD is also presented.

Abstract: A system and method of analyzing a powered device (PD) in a Power-over-Ethernet (PoE) system are presented. The system includes an Ethernet interface having a physical layer (PRY) chip capable of providing a signal pulse in addition to physical layer 1 functions. The system further includes a pulse transformer, coupled to the PRY chip, capable of relaying the signal pulse provided by the PRY chip to the PD via the transmit line and a second PRY chip. The first PRY chip receives one or more return pulse signals from the PD, analyzes characteristics such as voltage and/or frequency of the return pulse signal(s), and determines attributes of the PD based on those characteristics. The attributes can include powered device validity and power classification. A method of supplying power to a PD is also presented.

Abstract: A system and method of analyzing a powered device (PD) in a Power-over-Ethernet (PoE) system are presented. The system includes an Ethernet interface having a physical layer (PHY) chip capable of providing a signal pulse in addition to physical layer 1 functions. The system further includes a pulse transformer, coupled to the PHY chip, capable of relaying the signal pulse provided by the PHY chip to the PD via the transmit line and a second PHY chip. The first PHY chip receives one or more return pulse signals from the PD, analyzes characteristics such as voltage and/or frequency of the return pulse signal(s), and determines attributes of the PD based on those characteristics. The attributes can include powered device validity and power classification. A method of supplying power to a PD is also presented.

Abstract: An LED driver circuit is disclosed that can drive a plurality of LED strings that are arranged in parallel, each LED string having a plurality of component LEDs that are series-connected. The LED strings can be the same type of LEDs in each string, or have different types of LEDs from one string to another. The LED driver includes a voltage control loop that dynamically regulates the output voltage across the parallel arrangement of LED strings. The output voltage is dynamically adjusted to accommodate the LED string with the largest operational voltage drop. This enables LED displays to constructed using different types of LEDs strings, but still supply the LED strings in a power efficient manner. Further, each LED string also includes its own individual current regulation loop so that the current, and therefore brightness, of each LED string can be individually adjusted.

Abstract: An LED driver circuit is disclosed that can drive a plurality of LED strings that are arranged in parallel, each LED string having a plurality of component LEDs that are series-connected. The LED strings can be the same type of LEDs in each string, or have different types of LEDs from one string to another. The LED driver includes a voltage control loop that dynamically regulates the output voltage across the parallel arrangement of LED strings. The output voltage is dynamically adjusted to accommodate the LED string with the largest operational voltage drop. This enables LED displays to constructed using different types of LEDs strings, but still supply the LED strings in a power efficient manner. Further, each LED string also includes its own individual current regulation loop so that the current, and therefore brightness, of each LED string can be individually adjusted.

Abstract: Traditionally, system loads are placed in parallel with the battery. This simple topology wastes the available power if the USB power and/or wall adapter is present. Recent topologies have made some improvements by powering the load by the maximum available voltage. Thus, if a USB power source or wall adapter is present, the load is powered by them rather than the battery, thus improving the system efficiency. However, since the USB power and wall adapter power are current limited, if the load requires higher current than the current limited USB or adapter, then the entire system is powered at voltage of the battery. The present invention further improves the system efficiency by distinguishing the load and powering the constant power loads by the maximum voltage and placing the constant current loads in parallel with the battery.

Abstract: A system and method providing output voltage control in a power supply circuit. Various aspects of the present invention may comprise at least a first module adapted to receive an input DC voltage and at least one voltage control signal and output an output DC voltage that is a function of the input DC voltage and the voltage control signal. At least a second module may be adapted to receive a feedback signal representative of the output DC voltage and output the at least one voltage control signal as a function of at least the feedback signal. The second module may, for example, be a digital module adapted to generate the at least one voltage control signal utilizing digital active components. The second module may also, for example, utilize transistors and/or passive components controlled by the digital active components to generate the at least one voltage control signal.

Abstract: Traditionally, system loads are placed in parallel with the battery. This simple topology wastes the available power if the USB power and/or wall adapter is present. Recent topologies have made some improvements by powering the load by the maximum available voltage. Thus, if a USB power source or wall adapter is present, the load is powered by them rather than the battery, thus improving the system efficiency. However, since the USB power and wall adapter power are current limited, if the load requires higher current than the current limited USB or adapter, then the entire system is powered at voltage of the battery. The present invention further improves the system efficiency by distinguishing the load and powering the constant power loads by the maximum voltage and placing the constant current loads in parallel with the battery.

Abstract: A system and method of analyzing a powered device (PD) in a Power-over-Ethernet (PoE) system are presented. The system includes an Ethernet interface having a physical layer (PHY) chip capable of providing a signal pulse in addition to physical layer 1 functions. The system further includes a pulse transformer, coupled to the PHY chip, capable of relaying the signal pulse provided by the PHY chip to the PD via the transmit line and a second PHY chip. The first PHY chip receives one or more return pulse signals from the PD, analyzes characteristics such as voltage and/or frequency of the return pulse signal(s), and determines attributes of the PD based on those characteristics. The attributes can include powered device validity and power classification. A method of supplying power to a PD is also presented.

Abstract: A method and apparatus is disclosed for an internal control circuit that switches transistors rapidly on and off to stabilize the output voltage or current of a switch-mode power supply (SMPS). The internal control circuit uses analog and digital signals to regulate the output voltage of the switch-mode power supply. The internal control circuit adjusts the output voltage using pulse width modulation. The duty cycle of the pulse is based upon the comparison of the output voltage and a reference level.

Abstract: An LED driver circuit is disclosed that can drive a plurality of LED strings that are arranged in parallel, each LED string having a plurality of component LEDs that are series-connected. The LED strings can be the same type of LEDs in each string, or have different types of LEDs from one string to another. The LED driver includes a voltage control loop that dynamically regulates the output voltage across the parallel arrangement of LED strings. The output voltage is dynamically adjusted to accommodate the LED string with the largest operational voltage drop. This enables LED displays to constructed using different types of LEDs strings, but still supply the LED strings in a power efficient manner. Further, each LED string also includes its own individual current regulation loop so that the current, and therefore brightness, of each LED string can be individually adjusted.

Abstract: A system and method providing output voltage control in a power supply circuit. Various aspects of the present invention may comprise at least a first module adapted to receive an input DC voltage and at least one voltage control signal and output an output DC voltage that is a function of the input DC voltage and the voltage control signal. At least a second module may be adapted to receive a feedback signal representative of the output DC voltage and output the at least one voltage control signal as a function of at least the feedback signal. The second module may, for example, be a digital module adapted to generate the at least one voltage control signal utilizing digital active components. The second module may also, for example, utilize transistors and/or passive components controlled by the digital active components to generate the at least one voltage control signal.

Abstract: Method and circuitry for efficiently boosting voltage for low power supply applications. In one embodiment a phase boosting circuit that boosts a clock signal to substantially twice the power supply voltage level in a single half-cycle is implemented. The circuit eliminates the need for depletion transistors and can thus be implemented using conventional complementary metal-oxide-semiconductor (CMOS) fabrication processes. A novel voltage summing circuit allows the phase doubler to achieve greater boosting capability for applications with ultra low power supply voltages.