Patents by Inventor Farzaneh Yahyaei-Moayyed
Farzaneh Yahyaei-Moayyed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240069075Abstract: Techniques and mechanisms for sensing a voltage difference across two interconnect structures of a multi-chip packaged device. In an embodiment, the interconnect structures provide respective voltages to each of multiple integrated circuit (IC) chips of the packaged device. Switch circuitry of the packaged device is operable to provide any of multiple modes which each switchedly couple a voltage sensor to a different respective one of various sample point pairs of the interconnect structures. Control circuitry operates the switch circuitry to selectively provide one of the multiple modes based on an indication of a workload to be performed with one or more of the IC chips. In another embodiment, the voltage sensor senses the voltages each at a respective sample point of a sample point pair which corresponds to the selected mode of the switch circuitry.Type: ApplicationFiled: January 6, 2021Publication date: February 29, 2024Applicant: Intel CorporationInventors: Xiaoguo LIANG, Farzaneh YAHYAEI-MOAYYED, Nazar HAIDER, Nishi AHUJA, Jie YAN, Julio C. CINCO GALICIA
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Publication number: 20210183846Abstract: A processor module comprises an integrated circuit component attached to a power interposer. One or more voltage regulator modules attach to the power interposer via interconnect sockets and the power interposer routes regulated power signals generated by the voltage regulator modules to the integrated circuit component. Input power signals are provided to the voltage regulator from the system board via straight pins, a cable connector, or another type of connector. The integrated circuit component's I/O signals are routed through the power interposer to a system board via a socket located between the power interposer and the socket. Not having to route regulated power signals from a system board through a socket to an integrated circuit component can result in a system board with fewer layers, which can reduce overall system cost, as well as creating more area available in the remaining layers for I/O signal entry to the socket.Type: ApplicationFiled: February 25, 2021Publication date: June 17, 2021Applicant: Intel CorporationInventors: Jeffory L. Smalley, Thomas Holden, Russell J. Wunderlich, Farzaneh Yahyaei-Moayyed, Mohanraj Prabhugoud, Horthense Delphine Tamdem, Vijaya Boddu, Kaladhar Radhakrishnan, Timothy Glen Hanna, Krishna Bharath, Judy Amanor-Boadu, Mark A. Schmisseur, Srikant Nekkanty, Luis E. Rosales Galvan
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Patent number: 7212395Abstract: According to some embodiments, a capacitor includes a first external capacitor plane including a first at least one terminal of a first polarity, and a first internal capacitor plane including a second at least one terminal of the first polarity. The second at least one terminal of the first polarity may be electrically coupled to the first at least one terminal of the first polarity, and a total area of the second at least one terminal of the first polarity may be less than a total area of the first at least one terminal of the first polarity.Type: GrantFiled: December 28, 2004Date of Patent: May 1, 2007Assignee: Intel CorporationInventors: Yuan-Liang Li, David G. Figueroa, Farzaneh Yahyaei-moayyed, Dong Zhong
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Publication number: 20060139847Abstract: According to some embodiments, a capacitor includes a first external capacitor plane comprising a first at least one terminal of a first polarity, and a first internal capacitor plane comprising a second at least one terminal of the first polarity. The second at least one terminal of the first polarity may be electrically coupled to the first at least one terminal of the first polarity, and a total area of the second at least one terminal of the first polarity may be less than a total area of the first at least one terminal of the first polarity.Type: ApplicationFiled: December 28, 2004Publication date: June 29, 2006Inventors: Yuan-Liang Li, David Figueroa, Farzaneh Yahyaei-moayyed, Dong Zhong
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Patent number: 6975518Abstract: An electronic assembly includes one or more conductive clamps (302, 304, FIG. 3), which are used to supply current to an integrated circuit (IC) package (308). The conductive clamps are attached to a printed circuit (PC) board (312), which supplies the current to the IC package over one clamp, and receives returned current from the IC package over another clamp. Each clamp contacts a contact pad (330) on the surface of the PC board, and contacts another contact pad (334) on the top surface of the IC package. Vias (338, 339) and conductive planes (340, 342) within the package then carry current to and from an IC (e.g., IC 306) connected to the package. In another embodiment, the clamp (904, FIG. 9) holds a conductive structure (902) in place between the PC board contact pad (908) and the IC package contact pad (914), and current is carried primarily over the conductive structure, rather than over the clamp.Type: GrantFiled: May 28, 2003Date of Patent: December 13, 2005Assignee: Intel CorporationInventors: Kristopher Frutschy, Glenn E. Stewart, Farzaneh Yahyaei-Moayyed, Geoffrey L. Reid
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Patent number: 6877223Abstract: A method for fabricating a socket (300, FIG. 3) includes fabricating a conductive structure (310, FIG. 3) and embedding the conductive structure in a housing (302). The housing includes multiple openings (304) formed in the top surface. Each opening (304) provides access to conductive contacts (502, FIG. 5), which provide an electrical interface between a device that is inserted into the socket and the next level of interconnect (e.g., a PC board). In one embodiment, the embedded conductive structure (310) is electrically connected to one or more ground conducting contacts (708, FIG. 7B). The conductive structure includes column walls (312), which run in parallel with columns of contacts, and row walls (314), which run in parallel with rows of contacts and which intersect the column walls. In this manner, the conductive structure forms multiple chambers (402, FIG. 4).Type: GrantFiled: June 20, 2002Date of Patent: April 12, 2005Assignee: Intel CorporationInventors: David G. Figueroa, Chee-Yee Chung, Kristopher Frutschy, Farzaneh Yahyaei-Moayyed
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Patent number: 6784532Abstract: An integrated circuit including a die, a power terminal and a ground terminal all mounted onto a substrate. The power terminal including a body and a first extension projecting from the body, and the ground terminal including a body and a second extension projecting from the body. The second extension on the ground terminal being adjacent to the first extension on the power terminal to offset inductance that is generated by supplying current to the die through the power terminal.Type: GrantFiled: July 31, 2002Date of Patent: August 31, 2004Assignee: Intel CorporationInventors: Dong Zhong, Farzaneh Yahyaei-Moayyed, David G. Figueroa, Chris Baldwin, Jiangqi He, Yuan-Liang Li
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Publication number: 20040021215Abstract: An integrated circuit including a die, a power terminal and a ground terminal all mounted onto a substrate. The power terminal including a body and a first extension projecting from the body, and the ground terminal including a body and a second extension projecting from the body. The second extension on the ground terminal being adjacent to the first extension on the power terminal to offset inductance that is generated by supplying current to the die through the power terminal.Type: ApplicationFiled: July 31, 2002Publication date: February 5, 2004Applicant: Intel CorporationInventors: Dong Zhong, Farzaneh Yahyaei-Moayyed, David G. Figueroa, Chris Baldwin, Jiangqi He, Yuan-Liang Li
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Patent number: 6584685Abstract: A system and method for embedding power and ground planes in a pin grid array (PGA) socket is provided. Integrated circuit pins are inserted into multiple insertion holes of varying dimensions in the power and ground planes. When the cover of the socket is slidably moved, power pins touch the power plane and ground pins touch the ground plane. Decoupling capacitors are also affixed to the substrate. Thus, the power delivery performance of the overall central processing unit (CPU) package is improved. Moreover, the power and ground planes enhance the mechanical strength of the socket which reduces warpage.Type: GrantFiled: December 17, 2001Date of Patent: July 1, 2003Assignee: Intel CorporationInventors: Chee-Yee Chung, David Figueroa, Kris Frutschy, Bob Sankman, Farzaneh Yahyaei-Moayyed
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Patent number: 6586684Abstract: An electronic assembly includes one or more conductive clamps (302, 304, FIG. 3), which are used to supply current to an integrated circuit (IC) package (308). The conductive clamps are attached to a printed circuit (PC) board (312), which supplies the current to the IC package over one clamp, and receives returned current from the IC package over another clamp. Each clamp contacts a contact pad (330) on the surface of the PC board, and contacts another contact pad (334) on the top surface of the IC package. Vias (338, 339) and conductive planes (340, 342) within the package then carry current to and from an IC (e.g., IC 306) connected to the package. In another embodiment, the clamp (904, FIG. 9) holds a conductive structure (902) in place between the PC board contact pad (908) and the IC package contact pad (914), and current is carried primarily over the conductive structure, rather than over the clamp.Type: GrantFiled: June 29, 2001Date of Patent: July 1, 2003Assignee: Intel CorporationInventors: Kristopher Frutschy, Glenn E. Stewart, Farzaneh Yahyaei-Moayyed, Geoffery L. Reid
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Patent number: 6558181Abstract: A system and method for embedding power and ground planes in a pin grid array (PGA) socket is provided. Integrated circuit pins are inserted into multiple insertion holes of varying dimensions in the power and ground planes. When the cover of the socket is slidably moved, power pins touch the power plane and ground pins touch the ground plane. Decoupling capacitors are also affixed to the substrate. Thus, the power delivery performance of the overall central processing unit (CPU) package is improved. Moreover, the power and ground planes enhance the mechanical strength of the socket which reduces warpage.Type: GrantFiled: December 29, 2000Date of Patent: May 6, 2003Assignee: Intel CorporationInventors: Chee-Yee Chung, David Figueroa, Kris Frutschy, Bob Sankman, Farzaneh Yahyaei-Moayyed
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Publication number: 20030000739Abstract: An electronic assembly includes one or more conductive clamps (302, 304, FIG. 3), which are used to supply current to an integrated circuit (IC) package (308). The conductive clamps are attached to a printed circuit (PC) board (312), which supplies the current to the IC package over one clamp, and receives returned current from the IC package over another clamp. Each clamp contacts a contact pad (330) on the surface of the PC board, and contacts another contact pad (334) on the top surface of the IC package. Vias (338, 339) and conductive planes (340, 342) within the package then carry current to and from an IC (e.g., IC 306) connected to the package. In another embodiment, the clamp (904, FIG. 9) holds a conductive structure (902) in place between the PC board contact pad (908) and the IC package contact pad (914), and current is carried primarily over the conductive structure, rather than over the clamp.Type: ApplicationFiled: June 29, 2001Publication date: January 2, 2003Applicant: Intel CorporationInventors: Kristopher Frutschy, Glenn E. Stewart, Farzaneh Yahyaei-Moayyed, Geoffery L. Reid
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Publication number: 20020151218Abstract: A socket (300, FIG. 3) includes a housing (302) with multiple openings (304) formed in the top surface. Each opening (304) provides access to conductive contacts (502, FIG. 5), which provide an electrical interface between a device that is inserted into the socket and the next level of interconnect (e.g., a PC board). Embedded within the socket is a conductive structure (310, FIG. 3). In one embodiment, the conductive structure is electrically connected to one or more ground conducting contacts (708, FIG. 7B). The conductive structure includes column walls (312), which run in parallel with columns of contacts, and row walls (314), which run in parallel with rows of contacts and which intersect the column walls. In this manner, the conductive structure forms multiple chambers (402, FIG. 4). Each signal carrying and power conducting contact is positioned within a chamber.Type: ApplicationFiled: June 20, 2002Publication date: October 17, 2002Applicant: Intel CorporationInventors: David G. Figueroa, Chee-Yee Chung, Kristopher Frutschy, Farzaneh Yahyaei-Moayyed
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Publication number: 20020115330Abstract: A system and method for embedding power and ground planes in a pin grid array (PGA) socket is provided. Integrated circuit pins are inserted into multiple insertion holes of varying dimensions in the power and ground planes. When the cover of the socket is slidably moved, power pins touch the power plane and ground pins touch the ground plane. Decoupling capacitors are also affixed to the substrate. Thus, the power delivery performance of the overall central processing unit (CPU) package is improved. Moreover, the power and ground planes enhance the mechanical strength of the socket which reduces warpage.Type: ApplicationFiled: December 29, 2000Publication date: August 22, 2002Inventors: Chee-Yee Chung, David Figueroa, Kris Frutschy, Bob Sankman, Farzaneh Yahyaei-Moayyed
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Publication number: 20020115313Abstract: A system and method for embedding power and ground planes in a pin grid array (PGA) socket is provided. Integrated circuit pins are inserted into multiple insertion holes of varying dimensions in the power and ground planes. When the cover of the socket is sidably moved, power pins touch the power plane and ground pins touch the ground plane. Decoupling capacitors are also affixed to the substrate. Thus, the power delivery performance of the overall central processing unit (CPU) package is improved. Moreover, the power and ground planes enhance the mechanical strength of the socket which reduces warpage.Type: ApplicationFiled: December 17, 2001Publication date: August 22, 2002Inventors: Chee-Yee Chung, David Figueroa, Kris Frutschy, Bob Sankman, Farzaneh Yahyaei-Moayyed
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Patent number: 6428358Abstract: A socket (300, FIG. 3) includes a housing (302) with multiple openings (304) formed in the top surface. Each opening (304) provides access to conductive contacts (502, FIG. 5), which provide an electrical interface between a device that is inserted into the socket and the next level of interconnect (e.g., a PC board). Embedded within the socket is a conductive structure (310, FIG. 3). In one embodiment, the conductive structure is electrically connected to one or more ground conducting contacts (708, FIG. 7). The conductive structure includes column walls (312), which run in parallel with columns of contacts, and row walls (314), which run in parallel with rows of contacts and which intersect the column walls. In this manner, the conductive structure forms multiple chambers (402, FIG. 4). Each signal carrying and power conducting contact is positioned within a chamber.Type: GrantFiled: December 28, 2000Date of Patent: August 6, 2002Assignee: Intel CorporationInventors: David G. Figueroa, Chee-Yee Chung, Kristopher Frutschy, Farzaneh Yahyaei-Moayyed
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Publication number: 20020086568Abstract: A socket (300, FIG. 3) includes a housing (302) with multiple openings (304) formed in the top surface. Each opening (304) provides access to conductive contacts (502, FIG. 5), which provide an electrical interface between a device that is inserted into the socket and the next level of interconnect (e.g., a PC board). Embedded within the socket is a conductive structure (310, FIG. 3). In one embodiment, the conductive structure is electrically connected to one or more ground conducting contacts (708, FIG. 7). The conductive structure includes column walls (312), which run in parallel with columns of contacts, and row walls (314), which run in parallel with rows of contacts and which intersect the column walls. In this manner, the conductive structure forms multiple chambers (402, FIG. 4). Each signal carrying and power conducting contact is positioned within a chamber.Type: ApplicationFiled: December 28, 2000Publication date: July 4, 2002Inventors: David G. Figueroa, Chee-Yee Chung, Kristopher Frutschy, Farzaneh Yahyaei-Moayyed