Abstract: A technique for performing ray tracing operations is provided. The technique includes processing small bounding box nodes in a box intersection test circuit to generate intersection test results for the small bounding box nodes; and processing large bounding box nodes in the box intersection test circuit to generate intersection test results for the large bounding box nodes.

Abstract: A technique for performing ray tracing operations is provided. The technique includes processing small bounding box nodes in a box intersection test circuit to generate intersection test results for the small bounding box nodes; and processing large bounding box nodes in the box intersection test circuit to generate intersection test results for the large bounding box nodes.

Abstract: A technique for performing ray tracing operations is provided. The technique includes traversing through a bounding volume hierarchy to an instance node; performing an instance node transform using common circuitry; traversing to a leaf node of the bounding volume hierarchy; and performing an intersection test for the leaf node using the common circuitry.

Abstract: A technique for performing ray tracing operations is provided. The technique includes reading descendant-shared type metadata for a non-leaf node of a bounding volume hierarchy; identifying one or more culling types for a ray-intersection test for a ray; and determining whether to treat the non-leaf node as not intersected based on whether the one or more culling types includes at least one type specified by the descendant-shared type metadata.

Abstract: A technique for performing ray tracing operations is provided. The technique includes reading descendant-shared type metadata for a non-leaf node of a bounding volume hierarchy; identifying one or more culling types for a ray-intersection test for a ray; and determining whether to treat the non-leaf node as not intersected based on whether the one or more culling types includes at least one type specified by the descendant-shared type metadata.

Abstract: Techniques for performing multi-sample anti-aliasing operations are provided. The techniques include detecting an instruction for a multi-sample anti-aliasing load operation; determining a sampling rate of source data for the load operation, data storage format of the source data, and loading mode indicating whether the load operation requests same or different color components, or depth data; and based on the determined sampling rate, data storage format, and loading mode, load data from a multi-sample source into a register.

Abstract: Devices, systems, and methods for sampling partially resident texture data. An instruction which includes a residency map descriptor is received. The instruction is executed to retrieve partially resident texture data from a mipmap stored in a memory based on the residency map descriptor. The residency map descriptor includes a residency map.

Abstract: Isochronous data transfers guarantee data packets are received at a particular frequency and within a prespecified jitter-tolerance. Asynchronous data transfers guarantee data integrity by allowing missed or errant packets to be resent as many times as needed until an error-free packet may be reconstructed at the receiver. Isochronous transfers address real-time needs but do not address the data integrity issue. Asynchronous transfers address the data integrity issue but cannot guarantee error-free data packets will be available so as to meet a real-time constraint. The present invention provides method and apparatus enable isochronous data transfers with improved data integrity. Various link layer and transaction layer mechanisms are taught. An embodiment involving the IEEE 1394 bus specification is addressed in detail.

Abstract: A method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an apparatus containing DMA engines. The DMA engines process different contexts, also referred to as distinct logical data streams. The phase of a bus along with the status of DMA transactions are monitored. The phase and the status are used to dynamically allocate priorities to the DMA engines to maximize the efficiency in processing data.

Abstract: An integrated circuit that includes an improved architecture that reduces the interface between different blocks by minimizing the wire connections between the two blocks. Specifically, the two blocks are structured to transfer data between the two blocks using only the data bus and a common clock, thus eliminating the need for an address bus. Each block contains data registers used for storing data. The data registers in one block correspond to the registers in the second block, with each block being aware of the memory structure of the other block. When one block needs data from the data registers of the other block, it requests the data and the sending block places the contents of its data registers on the bus sequentially. The requesting block reads the data from the data bus at the appropriate time by counting the number of clock cycles from the time that the data was requested.

Abstract: A method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an apparatus containing DMA engines. The DMA engines process different contexts, also referred to as distinct logical data streams. The phase of a bus along with the status of DMA transactions are monitored. The phase and the status are used to dynamically allocate priorities to the DMA engines to maximize the efficiency in processing data.

Abstract: A method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an apparatus containing DMA engines. The DMA engines process different contexts, also referred to as distinct logical data streams. The phase of a bus along with the status of DMA transactions are monitored. The phase and the status are used to dynamically allocate priorities to the DMA engines to maximize the efficiency in processing data.

Abstract: A method and apparatus for receiving packets from a bus. A packet is received at an interface to the bus. The packet is parsed, and a determination is made whether to retain the packet from the parsing of the packet. The packet is placed in a buffer with a header. The packet is moved from the buffer to another bus using information located within the header, wherein repeated parsing of the packet to move the packet to another bus is unnecessary.

Abstract: A method for optimizing bus transactions in a data processing system is provided. A bus transaction optimizer receives an original bus transaction request which includes an original start address of a target memory for the original bus transaction, an original byte size for a number of bytes for the original bus transaction, and an original bus command for the original bus transaction. The bus transaction optimizer generates multiple bus transaction requests in response to a determination that the original byte size is greater than or equal to a predetermined multiple transfer byte size data value. The multiple bus transaction requests may include at least one high-performance bus transaction request and at least one low-performance bus transaction request.