Abstract: An integrated sensing device comprising an array of sensor processor cells capable of being arranged into a detection array: Each sensor processor cell comprises a sensing medium; at least one transconductance amplifier configured for feedforward template multiplication; at least one transconductance amplifier configured for feedback template weights; a plurality of local dynamic memory cells; a data bus for data transfer; and a local logic unit. The array of sensor processor cells, by responding to data control signals, is capable of transforming, reshaping, and modulating the original sensed image into varied represenations which include (and extend) traditional spatial and temporal processing transformations.

Abstract: An integrated sensing device comprising an array of sensor processor cells capable of being arranged into a detection array: Each sensor processor cell comprises a sensing medium; at least one transconductance amplifier configured for feedforward template multiplication; at least one transconductance amplifier configured for feedback template weights; a plurality of local dynamic memory cells; a data bus for data transfer; and a local logic unit. The array of sensor processor cells, by responding to data control signals, is capable of transforming, reshaping, and modulating the original sensed image into varied represenations which include (and extend) traditional spatial and temporal processing transformations.

Abstract: A self-programmable chip for real-time estimation, prediction, and control includes a reconfigurable array processing network for compatibility with Very Large Scale Integration (VLSI). The reconfigurable array processing network provides a feed-forward neural network and learning modules, wherein a synapse cell structure (10) provides synapse cells (100) having on-chip learning integrated therein. The chip has a control cell structure (20) including at least one control cell (110) providing digital memory and control modules supplying ordered signal routing functionality and operational modes for the chip.

Abstract: An integrated sensing device including array of sensor processor cells capable of being arranged into a detection an array. Each sensor processor cell includes a sensing medium; at least one transconductance amplifier configured for feedforward template multiplication; at least one transconductance amplifier configured for feedback template weights; a plurality of local dynamic memory cells; a data bus for data transfer; and a local logic unit. The array of sensor processor cells, by responding to data control signals, is capable of transforming, reshaping, and modulating the original sensed image into varied represenations which include (and extend) traditional spatial and temporal processing transformations.

Abstract: An integrated sensor processing cell device capable of transforming, reshaping, and modulating an original sensed image includes a sensing medium. At least one memory device stores weight bits. Multiplexers are associated with at least one of the memory devices. At least one transconductance amplifier is associated with at least one of the multiplexers. A multiple input logic gate, associated with at least one of the memory devices, is configured to store a signed pixel output derived from the sensing medium output.

Abstract: This invention unifies a set of statistical signal processing, neuromorphic systems, and microelectronic implementation techniques for blind separation and recovery of mixed signals. A set of architectures, frameworks, algorithms, and devices for separating, discriminating, and recovering original signal sources by processing a set of received mixtures and functions of said signals are described. The adaptation inherent in the referenced architectures, frameworks, algorithms, and devices is based on processing of the received, measured, recorded or otherwise stored signals or functions thereof. There are multiple criteria that can be used alone or in conjunction with other criteria for achieving the separation and recovery of the original signal content from the signal mixtures. The composition adopts both discrete-time and continuous-time formulations with a view towards implementations in the digital as well as the analog domains of microelectronic circuits.

Abstract: Signal separation processing includes a signal separation architecture defining a relationship between at least one input signal and at least one output signal. The signal separation architecture includes a state space representation that establishes a relationship between the input and output signals. At least one output signal is based on the signal separation architecture.

Abstract: The present invention relates to a sensor for measuring the instantaneous rate of mass flow and the cumulative mass flow in steady or unsteady flows of single-phase liquids or gases in a duct. By measuring the shear stress or the streamwise pressure gradient at the duct wall, and relating it to mass flow through solutions to the Navier Stokes equations of fluid mechanics, information on mass flow through the entire duct cross sectional area is deduced.

Abstract: A novel visual method and system for interacting with displays and all devices that use such displays. The system has three hardware elements, which are a display, a light sensor or camera that can register the display image and the pointing device or its effect on the display, and a pointing device that can be registered by or produces recognizable characteristics that can be registered by the light sensor or camera.

Abstract: A first feedforward network receives an input vector signal and a plurality of weight signals and forms an output vector signal based thereupon. A second feedforward network, substantially identical to the first feedforward network, receives a first learning vector signal and the weight signals and forms a learning output vector based thereupon. A weight updating circuit generates the weight signals in accordance with a back propagation updating rule. The weight signals are updated based upon the first learning vector signal and a second learning vector signal in response to receiving a first predetermined layer signal, and are updated based upon the first learning vector signal, the second learning vector signal, and the learning output vector signal in response to receiving a second predetermined layer signal. A back propagation feedback network receives the second learning vector signal and the weight signals and generates a back propagated error vector signal based thereupon.

Abstract: A neuron circuit and a neural network including a four quadrant analog multiplier/summer circuit constructed in field effect transistors. The neuron circuit includes the analog multiplier/summer formed of an operational amplifier, plural sets of four field effect transistors, an RC circuit and a double inverter. The multiplier/summer circuit includes a set of four identical field effect transistors for each product implemented. This produces a four quadrant multiplication if the four field effect transistors operate in the triode mode. The output of the multiplier/summer is the sum of these products. The neural network includes a plurality of these neuron circuits. Each neuron circuit receives an input and a set of synaptic weight inputs. The output of each neuron circuit is supplied to the corresponding feedback input of each neuron circuit. The multiplier/summer of each neuron circuit produces the sum of the product of each neuron circuit output and its corresponding synaptic weight.

Abstract: The present invention is a neural network circuit including a plurality of neuron circuits. Each neuron circuit has an input node for receiving an input signal, an output node for generating an output signal and a self-feedback control node for receiving a self-feedback signal. An interconnection device having an electrically controllable conductance is connected between the input nodes of each pair of neuron circuits. The neural network circuit is consequently programmable via the voltages applied to the self-feedback control nodes and the interconnection devices. Such programmability permits the neural network circuit to store certain sets of desirable steady states. In the preferred embodiment the individual neuron circuits and the interconnection devices are constructed in very large scale integration CMOS. Thus this neural network circuit can be easily constructed with large numbers of neurons.