Patents by Inventor Fatma Arzum Simsek-Ege

Fatma Arzum Simsek-Ege has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11063059
    Abstract: Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Srikant Jayanti, Fatma Arzum Simsek-Ege, Pavan Kumar Reddy Aella
  • Publication number: 20210193314
    Abstract: Systems, apparatuses, and methods related to medical device data analysis are described. In some examples, a medical device is implanted in a user of the medical device and the data generated by the medical device is not easily accessible to the user. In an example, a controller can be configured to receive, by a mobile device coupled to a medical device, data from the medical device, where the data is a part of a baseline dataset related to the medical device. The controller can be configured to receive different data from the medical device, where the different data is received from the medical device as the different data is generated by the medical device, analyze the data from the medical device and the different data generated by the medical device, and perform an action based on the analyzed data and the different data generated by the medical device.
    Type: Application
    Filed: August 10, 2020
    Publication date: June 24, 2021
    Inventors: Gitanjali T. Ghosh, Irene K. Thompson, Jessica M. Maderos, Hongmei Wang, Fatma Arzum Simsek-Ege, Kathryn H. Russo
  • Patent number: 11043534
    Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: June 22, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Publication number: 20210183866
    Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate. The first source/drain region and the second source/drain region are separated by the channel. The example apparatus further includes a gate separated from the channel by a dielectric material and an access line formed in a high aspect ratio trench connected to the gate. The access line includes a first titanium nitride (TiN) material formed in the trench, a metal material formed over the first TiN material, and a second TiN material formed over the metal material. The example apparatus further includes a sense line coupled to the first source/drain region and a storage node coupled to the second source/drain region.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Fatma Arzum Simsek-Ege, Clement Jacob
  • Publication number: 20210174840
    Abstract: Some embodiments include an integrated assembly having a memory array, and having digit lines extending along a first direction through the memory array. Insulative spacers are along sidewalls of the digit lines. The insulative spacers extend continuously along the digit lines through the memory array. Conductive regions are laterally spaced from the digit lines by intervening regions. The conductive regions are configured as segments spaced apart from one another along the first direction. The intervening regions include regions of the insulative spacers and include void regions adjacent the regions of the insulative spacers. The void regions are configured as void-region-segments which are spaced apart from one another along the first direction by insulative structures. Storage-elements are associated with the conductive regions. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 10, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Naveen Kaushik, Fatma Arzum Simsek-Ege, Deepak Chandra Pandey
  • Patent number: 10991701
    Abstract: Described are methods for forming multi-component conductive structures for semiconductor devices. The multi-component conductive structures can include a common metal, present in different percentages between the two components of the conductive structures. As described example, multiple components can include multiple ruthenium materials having different percentages of ruthenium. In some applications, at least a portion of one of the ruthenium material components will be sacrificial, and removed in subsequent processing.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Eric Blomiley
  • Publication number: 20210066307
    Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example method may include patterning a working surface of a semiconductor wafer. The method may further include performing a vapor etch on a first dielectric material at the working surface to recess the first dielectric material to a first intended depth of an opening relative to the working surface and to expose a second dielectric material on a sidewall of the opening. The method may further include performing a wet etch on the second dielectric material to recess the second dielectric material to the intended depth.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 4, 2021
    Inventors: Vivek Yadav, Fatma Arzum Simsek-Ege, Sanjeev Sapra, Thomas A. Figura, Kangle Li
  • Publication number: 20210035979
    Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. The gate includes noble metal nanoparticles. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region.
    Type: Application
    Filed: October 8, 2020
    Publication date: February 4, 2021
    Inventors: Fatma Arzum Simsek-Ege, Kamal M. Karda, Haitao Liu
  • Publication number: 20210028308
    Abstract: An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.
    Type: Application
    Filed: July 25, 2019
    Publication date: January 28, 2021
    Inventors: Fatma Arzum Simsek-Ege, Steve V. Cole, Scott J. Derner, Toby D. Robbs
  • Publication number: 20210013305
    Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.
    Type: Application
    Filed: July 11, 2019
    Publication date: January 14, 2021
    Inventors: Kamal M. Karda, Haitao Liu, Si-Woo Lee, Fatma Arzum Simsek-Ege, Deepak Chandra Pandey, Chandra V. Mouli, John A. Smythe, III
  • Patent number: 10879259
    Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jie Sun, Zhenyu Lu, Roger W. Lindsay, Brian Cleereman, John Hopkins, Hongbin Zhu, Fatma Arzum Simsek-Ege, Prasanna Srinivasan, Purnima Narayanan
  • Patent number: 10854611
    Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Suraj J. Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
  • Patent number: 10847516
    Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Suraj J. Mathew, Raghunath Singanamalla, Fawad Ahmed, Kris K. Brown, Vinay Nair, Gloria Yang, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
  • Patent number: 10847527
    Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, John Hopkins, Srikant Jayanti
  • Patent number: 10818666
    Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. The gate includes noble metal nanoparticles. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Kamal M. Karda, Haitao Liu
  • Publication number: 20200258910
    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.
    Type: Application
    Filed: April 28, 2020
    Publication date: August 13, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Meng-Wei Kuo, John D. Hopkins
  • Patent number: 10672785
    Abstract: Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels. Regions of the insulative levels remain as ledges which separate adjacent cavities from one another. Material is removed from the ledges to thin the ledges, and then charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative levels and conductive levels. Cavities extend into the conductive levels. Ledges of the insulative levels separate adjacent cavities from one another. The ledges are thinned relative to regions of the insulative levels not encompassed by the ledges. Charge-blocking dielectric and charge-storage structures are within the cavities.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Meng-Wei Kuo, John D. Hopkins
  • Publication number: 20200144331
    Abstract: Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a source material, a buffer material, a select gate drain (SGD), and a memory stack arranged between the source material and the SGD. The memory stack comprises alternating levels of conductor materials and dielectric materials. A continuous channel-fill material forms a cell pillar that is continuous from the source material to at least a level corresponding to the SGD.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Inventors: Fatma Arzum Simsek-Ege, Krishna K. Parat
  • Publication number: 20200135748
    Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: Fatma Arzum Simsek-Ege, Krishna K. Parat, Luan C. Tran, Meng-Wei Kuo, Yushi Hu
  • Patent number: 10600807
    Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Jie Sun, Fatma Arzum Simsek-Ege