Patents by Inventor Fausto Piazza
Fausto Piazza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230058720Abstract: The present description relates to a method of manufacturing an interconnection structure of an integrated circuit intended to be encapsulated in an encapsulation resin in contact with a first surface of a protection layer. The protection layer is resting on a first surface of the interconnection structure. The interconnection structure comprising copper interconnection elements extending at least partly through an insulating layer and flush with the first surface of said interconnection structure. The manufacturing method includes a step of structuring of the protection layer or a step of forming of the protection layer with a structuring. The structuring step or the forming step is adapted to structuring the first surface of the protection layer in the form of an alternation of ridges and troughs.Type: ApplicationFiled: August 10, 2022Publication date: February 23, 2023Applicant: STMicroelectronics (Crolles 2) SASInventors: Sylvie DEL MEDICO, Jean-Christophe GRENIER, Jean-Christophe GIRAUDIN, Philippe KOWALCZYK, Fausto PIAZZA
-
Publication number: 20230032898Abstract: A memory cell includes a substrate with a semiconductor region and an insulating region. A first insulating layer extends over the substrate. A phase change material layer rests on the first insulating layer. The memory cell further includes an interconnection network with a conductive track. A first end of a first conductive via extending through the first insulating layer is in contact with the phase change material layer and a second end of the first conductive via is in contact with the semiconductor region. A first end of a second conductive via extending through the first insulating layer is in contact with both the phase change material layer and the conductive track, and a second end of the second conductive via is in contact only with the insulating region.Type: ApplicationFiled: July 27, 2022Publication date: February 2, 2023Applicants: STMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SASInventors: Paolo Giuseppe CAPPELLETTI, Fausto PIAZZA, Andrea REDAELLI
-
Publication number: 20230006132Abstract: A method for making a phase change memory includes a step of forming an array of phase change memory cells, with each cell being separated from neighboring cells in the same line of the array and from neighboring cells in the same column of the array, by the same first distance. The method further includes a step of etching one memory cell out of N, with N being at least equal to 2, in each line or each column.Type: ApplicationFiled: June 22, 2022Publication date: January 5, 2023Applicant: STMicroelectronics (Crolles 2) SASInventors: Laurent FAVENNEC, Fausto PIAZZA
-
Patent number: 11495609Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.Type: GrantFiled: November 9, 2020Date of Patent: November 8, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Fausto Piazza, Sebastien Lagrasta, Raul Andres Bianchi, Simon Jeannot
-
Publication number: 20210057426Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.Type: ApplicationFiled: November 9, 2020Publication date: February 25, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Fausto PIAZZA, Sebastien LAGRASTA, Raul Andres BIANCHI, Simon JEANNOT
-
Patent number: 10833094Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.Type: GrantFiled: April 17, 2018Date of Patent: November 10, 2020Assignee: STMicroelectronics (Crolles 2) SASInventors: Fausto Piazza, Sebastien Lagrasta, Raul Andres Bianchi, Simon Jeannot
-
Publication number: 20180233511Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.Type: ApplicationFiled: April 17, 2018Publication date: August 16, 2018Applicant: STMicroelectronics (Crolles 2) SASInventors: Fausto PIAZZA, Sebastien LAGRASTA, Raul Andres BIANCHI, Simon JEANNOT
-
Patent number: 9978764Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.Type: GrantFiled: April 20, 2016Date of Patent: May 22, 2018Assignee: STMicroelectronics (Crolles 2) SASInventors: Fausto Piazza, Sebastien Lagrasta, Raul Andres Bianchi, Simon Jeannot
-
Publication number: 20170186759Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.Type: ApplicationFiled: April 20, 2016Publication date: June 29, 2017Applicant: STMicroelectronics (Crolles 2) SASInventors: Fausto Piazza, Sebastien Lagrasta, Raul Andres Bianchi, Simon Jeannot
-
Patent number: 8450199Abstract: Different types of transistors, such as memory cells, higher voltage, and higher performance transistors, may be formed on the same substrate. A transistor may be formed with a first polysilicon layer covered by a dielectric. A second polysilicon layer over the dielectric may be etched to form a sidewall spacer on the gate of the transistor. The sidewall spacer may be used to form sources and drains and to define sub-lithographic lightly doped drains. After removing the spacer, the underlying dielectric may protect the lightly doped drains.Type: GrantFiled: December 22, 2008Date of Patent: May 28, 2013Assignee: Micron Technology, Inc.Inventors: Fausto Piazza, Alfonso Maurelli
-
Publication number: 20100155852Abstract: Different types of transistors, such as memory cells, higher voltage, and higher performance transistors, may be formed on the same substrate. A transistor may be formed with a first polysilicon layer covered by a dielectric. A second polysilicon layer over the dielectric may be etched to form a sidewall spacer on the gate of the transistor. The sidewall spacer may be used to form sources and drains and to define sub-lithographic lightly doped drains. After removing the spacer, the underlying dielectric may protect the lightly doped drains.Type: ApplicationFiled: December 22, 2008Publication date: June 24, 2010Inventors: Fausto Piazza, Alfonso Maurelli
-
Publication number: 20070287290Abstract: Electrically non-active structures are formed for an electronic circuit to make uniform a surface above a semiconductor substrate. The electronic circuit includes first electrically active structures comprising conductive elements of a first height projecting from the semiconductor substrate, and second electrically active structures comprising conductive elements of a second height projecting from the semiconductor substrate. The first height is different from the second height. The electrically non-active structures are formed by identifying, among the electrically non-active structures, a first group of electrically non-active structures formed within areas that substantially extend for a radius around each electrical component belonging to the second electrically active structures. The method further includes identifying, among the electrically non-active structures, a second group of electrically non-active structures not belonging to the first group of electrically non-active structures.Type: ApplicationFiled: May 29, 2007Publication date: December 13, 2007Applicant: STMicroelectronics S.r.l.Inventors: Alfonso Maurelli, Daniela Peschiaroli, Fausto Piazza, Carlo Vigiani, Paola Zabberoni
-
Patent number: 6627928Abstract: A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.Type: GrantFiled: October 1, 2002Date of Patent: September 30, 2003Assignee: STMicroelectronics S.r.l.Inventors: Daniela Peschiaroli, Alfonso Maurelli, Elisabetta Palumbo, Fausto Piazza
-
Publication number: 20030032244Abstract: A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.Type: ApplicationFiled: October 1, 2002Publication date: February 13, 2003Applicant: STMicroelectronics S.r.I.Inventors: Daniela Peschiaroli, Alfonso Maurelli, Elisabetta Palumbo, Fausto Piazza
-
Patent number: 6482698Abstract: A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.Type: GrantFiled: March 26, 2001Date of Patent: November 19, 2002Assignee: STMicroelectronics S.r.l.Inventors: Daniela Peschiaroli, Alfonso Maurelli, Elisabetta Palumbo, Fausto Piazza
-
Publication number: 20010049166Abstract: A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.Type: ApplicationFiled: March 26, 2001Publication date: December 6, 2001Applicant: STMicroelectronics S.r.l.Inventors: Daniela Peschiaroli, Alfonso Maurelli, Elisabetta Palumbo, Fausto Piazza