Abstract: Several systems and methods are described for accessing one of multiple groups of peripheral devices. One of the systems includes a host system, multiple peripheral devices, and a host adapter. The peripheral devices are arranged to form multiple groups, each group including at least one peripheral device. The host system is coupled to the peripheral devices via the host adapter, and accesses the peripheral devices via the host adapter. The peripheral devices of each group receive a group access signal for controlling accesses from the host system. The host adapter includes a control register and signal routing logic. The signal routing logic is coupled to the control register and to each of the groups of peripheral devices. The control register stores a value for selecting one of the groups of peripheral devices. The host system may include a central processing unit (CPU) configured to write the value to the control register.

Abstract: One embodiment of a storage controller is described including a controller memory, one or more central processing units (CPUs), and a host bus adapter all coupled to a controller bus. The one or more CPUs are configured to produce data routing information dependent upon a data transfer command which directs a transfer of data between a host computer and one or more storage devices. The host bus adapter includes a receive unit and a transmit unit adapted for coupling to a transmission medium. The host bus adapter receives the data routing information, and forwards data associated with the data transfer command from the receive unit to the transmit unit dependent upon the data routing information such that the data associated with the data transfer command is not conveyed upon the controller bus and is not stored within the controller memory.

Abstract: A network and storage I/O device is described for use with a host computer system having a system bus coupled to a host processor and a main memory to provide a high bandwidth network server system. The network and storage I/O device includes a plurality of network controllers to communicate with client computers connected over a network, a plurality of storage controllers to transfer data to and from storage devices, at least one memory element to temporarily store data transferred between the network controllers and the storage controllers and a crossbar switch having a plurality of nodes to interconnect the plurality of network controllers, the plurality of storage controllers and the at least one memory element. The network and storage I/O device also includes a bridge coupled between one of the nodes and the system bus of the host computer.

Abstract: One embodiment of a transfer node is described, including a first channel port adapted for coupling to a host computer, a second channel port adapted for coupling to a storage controller and one or more storage devices, a central processing unit (CPU) coupled to the first and second channel ports, and a memory coupled to the CPU. The transfer node receives data routing information associated with a data transfer command from the storage controller via the second channel port, wherein the data transfer command directs a transfer of data between the host computer and the one or more storage devices. The transfer node stores the data routing information within the memory, and routes data associated with the data transfer command between the first and second channel ports using the data routing information stored within the memory.

Abstract: A variably positionable electrical connector provides a direct interface for a disk drive or other electrical device to a printed circuit board (PCB), backplane or motherboard of a computer system. The connector has a base (which may comprise a PCB or backplane) and a housing that slides relative to the base to allow the housing to be positioned according to the spacing between the electrical device's power and signal connectors. The housing includes multiple electrical contacts that receive or engage corresponding contacts of the device. Conductors that are electrically coupled to the computer system extend from the base and include portions that are aligned substantially parallel to a direction in which the housing can slide. The housing contacts slidably engage the parallel portions of the conductors and, as the housing is moved, the housing contacts slidably maintain electrical contact with the conductors.

Abstract: A method and apparatus may be employed for maintaining cooling efficiency during air mover failure. An electrical enclosure may include a heat-generating thermal load, multiple air movers configured to remove heat from the thermal load, and a backward-airflow reducing device configured to reduce the amount of air that can be drawn backwards through one of the air movers if that air mover fails. The backward-airflow reducing device may be a valve configured to open while the air mover if functioning and to close when the air mover is not functioning.

Abstract: Various methods and systems for cooling high-density arrangements of disk drives are disclosed. A disk drive enclosure includes several stacked layers of disk drives and one or more air movers. Some of the air movers are configured to cool the disk drives by creating an airflow. The disk drives are configured to operate as a network or computer storage system. Instead of being arranged in a traditional, aligned arrangement, the disk drives are arranged in an offset or staggered arrangement so that at least one disk drive in a first layer is offset from an overlapping disk drive in a second layer. The offset is in a direction parallel to the plane that includes the first layer. As a result, at least part of one of the disk drives in the arrangement is exposed to more of the airflow than it would be exposed to in an aligned arrangement.

Abstract: A substrate for packaging a storage or server system may include one or more sections of the substrate configured to hold a two-dimensional array of disk drives. Another section of this substrate may be configured to hold circuitry for accessing the array of disk drives. This circuitry may include one or more processors. The substrate also includes a first plurality of ribs positioned in the first access of the substrate. The first plurality of ribs separate the sections from one another. The section configured to hold the control circuitry may also be configured to hold one or more power supplies for supplying power to the array of disk drives and control circuitry. This section, as well as other sections, may be divided in two by one or more additional ribs in a transverse direction. The substrate may be configured to be mounted in a cage or rack and may include an edge connector at one edge of the substrate to provide electrical connectivity to a back plane in the cage or rack.

Abstract: A system and a method to transfer data between a host computer and a storage device. The storage controller architecture is organized into its functional modules based on whether a module primarily performs a control function or a data transfer function. The data paths that connect various functional units (for example, switching unit, parity logic, memory module, etc.) may then be sized to the required bandwidth. This effectively makes the iops (I/O operations per second) and bandwidth capability of a storage controller scalable independently of each other. A data transfer command from a host computer is decoded and translated into one or more data transfer commands by the control module in the storage controller. The control module then sends a list of translated commands to the host. Parity calculation, caching, one or more RAID levels and other relevant data transfer information may also be included as part of the translated set of commands.

Abstract: An apparatus and methods are provided for interfacing a disk drive to a computer system without requiring conventional power and signal cables between the apparatus and the disk drive. An interface assembly comprises a set of power connectors and a set of signal connectors for receiving corresponding connectors of a disk drive. One or more of the assembly connectors (e.g., the power connectors) are translatable in at least one dimension so that the assembly is not limited to disk drives having a particular spacing between their power and signal connectors. The interface assembly may comprise two printed circuit boards (PCB) or backplanes—one for the power connectors and one for the signal connectors. In this configuration one of the PCBs defines a set of apertures through which the connectors of the other PCB protrude, and the other PCB is slidably or otherwise translatable along a portion of the length of the first PCB so that the protruding connectors are movable within the apertures.

Abstract: Several embodiments of a computer system are described which achieve separation of control and data paths during data transfer operations, thus allowing independent scalability of storage system performance factors (e.g., storage system ops and data transfer rate). In one embodiment, the computer system includes a data switch coupled between a host computer and one or more storage devices. A storage controller for managing the storage of data within the one or more storage devices is coupled to the switch. The switch includes a memory for storing data routing information generated by the controller, and uses the data routing information to route data directly between the host computer and the one or more storage devices such that the data does not pass through the storage controller. Within the computer system, information may be conveyed between the host computer, the switch, the one or more storage devices, and the storage controller according to a two party protocol such as the Fibre Channel protocol.

Abstract: A scalable performance storage architecture. The input/output operations per second (iops) and the data transfer rate are two very important performance measures of a storage system. Command and status information require little bandwidth, whereas data transfer is limited by the bandwidth of the storage controller busses, memory, etc. This invention first organizes the storage controller architecture into its functional units. The data paths that connect various functional units (for example, switching unit, parity logic, memory module, etc.) may then be sized to the required bandwidth. This effectively makes the iops and bandwidth capability of a storage controller scalable independently of each other, resulting in a selectively scalable storage system architecture. The system designer may increase the number of CPU's in a storage controller (for more iops) or the data bandwidth (for high aggregate data transfer rate) independently of each other.

Abstract: An efficient memory retrieval/storage schemes for a fault tolerant memory control system for a computer system having a host processor, a mass storage memory and a system interconnect. The memory control system includes a primary memory controller and a backup memory controller with taps between the memory controllers to increase fault tolerance. Data is transferred between the host processor and the mass storage memory in the form of data packets. During a write operation, instead of receiving a data packet from the host processor, storing the data content, retrieving the data and then generating a new data packet for the mass storage memory, the memory controller redirects the data packets without the need to copy the data into the controller cache.

Abstract: A fault tolerant memory control system is provided for a computer system having a host processor, a memory and a system interconnect. The memory control system includes a primary memory controller and a backup memory controller with a tap coupled to the interconnect. Data is transferred from the host processor to the memory in the form of data packets. First, the host processor writes to the memory by sending a data packet to the primary memory controller which then caches the data from the data packet. The backup memory controller taps the interconnect to obtain a backup copy of the data packet as the data packet is being sent from the host processor to the primary memory controller which caches the data from the backup copy of the data packet. If the primary memory controller is functional, the primary memory controller sends the data to the memory via a primary path coupling the primary memory controller to the memory. Conversely, if the primary memory controller fails, i.e.