Abstract: A plasma processing chamber for depositing a film on an underside surface of a wafer, includes a showerhead pedestal. The showerhead pedestal includes a first zone and a second zone. The first zone is configured for depositing a first film to the underside surface of the wafer and the second zone is configured for depositing a second film to the underside surface of the wafer.

Abstract: Semiconductor processing tools with wafer back-side processing capabilities are disclosed. Such tools may be configured to only contact wafers being processed through edge contact, as opposed to underside/planar contact. Such tools may also include wafer-centering features that may allow such wafers to be precisely centered with regard to a particular wafer processing station thereof.

Abstract: A high-stress, thermally-stable compressive nitride film is deposited on a semiconductor substrate. The compressive nitride film may be deposited by plasma-enhanced chemical vapor deposition (PECVD) under conditions that produce a compressive nitride film with high compressive film stress and with a minimal stress shift when exposed to a temperature greater than a deposition temperature of the compressive nitride film. In some implementations, the compressive nitride film is a silicon nitride film. The PECVD conditions may reduce a number of Si—H bonds in the silicon nitride to obtain improved thermal stability. In some implementations, the high-stress, thermally-stable nitride film is deposited on a backside of the semiconductor substrate for wafer bow compensation.

Abstract: A plasma processing chamber for depositing a film on an underside surface of a wafer, includes a showerhead pedestal. The showerhead pedestal includes a first zone and a second zone. The first zone is configured for depositing a first film to the underside surface of the wafer and the second zone is configured for depositing a second film to the underside surface of the wafer.

Abstract: A plasma processing chamber for depositing a film on an underside surface of a wafer, includes showerhead pedestal. The showerhead pedestal includes a first zone and a second zone. An upper separator fin is disposed over a top surface of the showerhead pedestal and a lower separator fin is disposed under the top surface of the showerhead pedestal and aligned with the upper separator fin. The first zone is configured for depositing a first film to the underside surface of the wafer and the second zone is configured for depositing a second film to the underside surface of the wafer. In another embodiment, a top surface of the showerhead pedestal may be configured to receive a masking plate instead of the upper separator fin. The masking plate is configured with a first area that has openings and a second area that is masked. The first areas is used to provide the process gas to a portion of the underside surface of the wafer for depositing a film.

Abstract: Multi-station processing tools with station-varying support features for backside processing are provided. The support features in a first station may hold a wafer at a first set of points during backside deposition, blocking backside deposition, etching, or other processing at those points. The support features in a second station may hold a wafer at a second set of points that don’t overlap with the first set of points.

Abstract: A carrier wafer for receiving a wafer and supporting the wafer during semiconductor processing operations. The carrier wafer includes an annular ring surface and a pocket, the pocket being defined in a center of the carrier wafer and including a step defined by a sidewall extending between the annular ring surface and a top surface of the pocket.

Abstract: Carrier rings with radially-varied plasma impedance are provided herein. In some embodiments, a carrier ring may include an outer ring that holds a removable inner ring. The outer ring may be formed of a dielectric material such as ceramic. The inner ring may be formed of a metal such as aluminum to provide a desired impedance. In some other embodiments, a carrier ring is formed from a single piece with radially-varying impedances.

Abstract: A method of controlling wafer bow in an integrated circuit fabrication process may include characterizing the wafer bow in response to performing one or more first fabrication processes to an active side of an integrated circuit wafer. Determining one or more second fabrication processes, to be applied to a back side of the integrated circuit wafer, to bring the wafer bow to below a predetermined threshold based on the one or more first fabrication processes the method may additionally include performing the one or more second fabrication processes on the back side of the integrated circuit wafer.

Abstract: Localized stresses can be modulated in a film deposited on a bowed semiconductor substrate by selectively and locally curing the film by ultraviolet (UV) radiation. A bowed semiconductor substrate can be asymmetrically bowed. A UV-curable film is deposited on the front side or the backside of the bowed semiconductor substrate. A mask is provided between the UV-curable film and a UV source, where openings in the mask are patterned to selectively define exposed regions and non-exposed regions of the UV-curable film. Exposed regions of the UV-curable film modulate localized stresses to mitigate bowing in the bowed semiconductor substrate.

Abstract: A plasma processing chamber for depositing a film on an underside surface of a wafer, includes showerhead pedestal. The showerhead pedestal includes a first zone and a second zone. An upper separator fin is disposed over a top surface of the showerhead pedestal and a lower separator fin is disposed under the top surface of the showerhead pedestal and aligned with the upper separator fin. The first zone is configured for depositing a first film to the underside surface of the wafer and the second zone is configured for depositing a second film to the underside surface of the wafer. In another embodiment, a top surface of the showerhead pedestal may be configured to receive a masking plate instead of the upper separator fin. The masking plate is configured with a first area that has openings and a second area that is masked. The first areas is used to provide the process gas to a portion of the underside surface of the wafer for depositing a film.

Abstract: A processing chamber includes: a lower portion; an upper portion that covers the lower portion; a pedestal that is located within the lower portion, to vertically support a substrate above a top surface of the pedestal to distribute a precursor between the top surface and a first surface of the substrate, the pedestal configured to be electrically connected to one of a ground potential and a radio frequency potential; a grid that is coupled to the upper portion and that is configured to be electrically connected to the other one of the ground potential and the radio frequency potential; a window that covers an opening in the upper portion; and an infrared light source configured to transmit infrared light through the window and the grid to a second surface of the substrate. The second surface of the substrate is opposite the first surface of the substrate.

Abstract: Methods for reducing warpage of bowed semiconductor substrates, particularly saddle-shaped bowed semiconductor substrates, are provided herein. Methods involve depositing a bow compensation layer by plasma enhanced chemical vapor deposition on the backside of the bowed semiconductor substrate by region, such as by quadrants, to form a compressive film on a tensile substrate and a tensile film on a compressive substrate. Methods involve flowing different gases from different nozzles on a surface of a showerhead to deliver various gases by region in a one-step operation or flowing gases in a multi-step process by shielding regions of the showerhead during delivery of gases to deliver specific gases from non-shielded regions onto regions of the bowed semiconductor substrate by alternating between rotating the semiconductor substrate and flowing gases to the backside of the bowed semiconductor substrate.

Abstract: Methods for reducing warpage of bowed semiconductor substrates, particularly saddle-shaped bowed semiconductor substrates, are provided herein. Methods involve depositing a bow compensation layer by plasma enhanced chemical vapor deposition on the backside of the bowed semiconductor substrate by region, such as by quadrants, to form a compressive film on a tensile substrate and a tensile film on a compressive substrate. Methods involve flowing different gases from different nozzles on a surface of a showerhead to deliver various gases by region in a one-step operation or flowing gases in a multi-step process by shielding regions of the showerhead during delivery of gases to deliver specific gases from non-shielded regions onto regions of the bowed semiconductor substrate by alternating between rotating the semiconductor substrate and flowing gases to the backside of the bowed semiconductor substrate.