Abstract: A method of testing a two-input multiplier, adder, or subtractor implementation for stuck-at faults includes a multi-step procedure for iteratively exercising all input and output permutations, and pseudo-exhaustively exercising all internal nodes. The method of testing a multiplier, adder, or subtractor involves logically partitioning the multiplication, addition, or subtraction into several smaller but identical independent operations. This logical partitioning of operations ensures that the output result will consist of several smaller identical results if the unit under test is functioning properly. Because the several smaller results are identical, comparing the smaller results to each other detects any failures internal to the multiplier, adder, or subtractor under test. The logically partitioned operations are repeated for multiple input setting to ensure a high level of fault coverage. In the testing of a multiplier, a four step iterative method fully exercises the multiplier.

Abstract: A set/reset scan flip-flop circuit normally inhibits set/reset operations in the scan mode, but allows a set/reset occurring in the last scan cycle to pass through. The circuit includes a multiplexer that receives a data signal and a scan signal. The scan signal is selected as the multiplexer output when Test Enable, which serves as the multiplexer select signal, is active. The Test Enable signal and the set/reset signal are provided as inputs to an OR gate such that, if Test Enable is active high, then the OR gate output is also high. The OR gate output is connected to the set/reset pin of a flip-flop. The multiplexer output drives the data input of the flip-flop. Therefore, assuming that the set/reset signal is active low, when in the scan mode, i.e., Test Enable is active high, the OR gate blocks the set/reset signal from the flip-flop. However, if set/rest goes active low in the last scan cycle, then the low-going Test Enable allows the set/rest to pass through.