Abstract: An integrated circuit implemented utilizing scan design for test techniques includes a plurality of bus driver circuits. Each bus driver circuit has a driver output connected to a bus to provide an associated driver output signal to the bus. Each bus driver circuit also includes a high impedance control node such that an input control signal having a first logic state applied to the control node enables the bus driver circuit to provide an associated driver output signal having either a high logic state or a low logic state. An input control signal having a second logic state applied to the control node causes the bus driver circuit to provide an associated driver output signal that has a high impedance state. The circuit also includes a plurality of scan registers coupled as a scan chain such that the scan chain responds to a scan test enable signal having the second logic state by initiating a scan-in operation in which test data is sequentially shifted into the scan registers in the scan chain.

Abstract: The scan flip-flop that controls a bi-directional or a switchable high-impedance driver is implemented so that, when a logic value on a first input is latched in response to a first clock signal, and a logic value on a second input is latched in response to a second clock signal, both logic values are output during the second clock period.

Abstract: Data or its inverse, is written into a regular structure, such as a RAM, while stepping through the address range. The data is then read out and a determination is made as to success or failure. The scheme is based upon a Johnson counter being the source of the data, or its inverse. This style of counting has the unique property that, every time a "count" takes place, the parity associated with the Johnson counter output will "toggle," since only one bit is allowed to change. Reliance on this parity toggling determines possible failures.

Abstract: A circuit including analog circuitry, digital circuitry partitioned from the analog circuitry, and a boundary scan cell chain along the boundary between the analog and digital circuitry. The chain can be controlled to decouple the analog circuitry from the digital circuitry and supply selected test signals to nodes along the boundary between the analog and digital circuitry during testing. Typically, the circuit is an integrated circuit having external pins for asserting signals directly to and receiving signals directly from each of the analog circuitry, digital circuitry, and boundary scan cell chain. Preferably, each cell of the chain comprises a first multiplexer, a flip-flop, and a second multiplexer having an input coupled to the flip-flop's output, another input coupled to one of the analog circuitry and the digital circuitry, and an output coupled to another of the analog circuitry and the digital circuitry.

Abstract: A testing circuit for use in testing X number of portions of circuitry embedded within a larger circuit. The testing circuit includes Y number of scan flip-flops which each have a normal data input, a scan data input, a data select input, a clock input and a data output. The scan flip-flops are serially coupled together such that the scan data input of a first flip-flop forms a serial data input for the testing circuit, the data output of a last flip-flop forms a serial data output for the testing circuit, the scan data input of each remaining flip-flop is connected to the data output of a previous flip-flop, the normal data input of at least one of the scan flip-flops forms an unload bus, and the data select signal of at least one of the scan flip-flops forms a test enable signal which enables one of the serial data input and the unload bus. Also included are Y number of latches which each have a data input, a clock input and a data output.

Abstract: Multiple embedded RAMs are tested, one at a time, for stuck at faults, including multibit faults. Parity for the RAMs is also tested and tests are performed for marginal read/write problems by changing clock frequency. A lockup mechanism yields the failing address. To accomplish the test, the RAM write address is written as data and then read back. Since the address is written as data, the expected result in a read operation is known. Thus, failures are predicted by comparing the reference address in a read cycle with the data read from the RAM. This operation is then repeated by writing the inverse write address as data. Through the two sets of write/read/compare operations, every RAM bit is toggled. After performing the two operations for one RAM, the procedure is repeated for each RAM until all have been tested. In a second embodiment, multiple embedded RAMs are tested simultaneously with the same address and data lines going to all RAMs.