Abstract: Examples of the present disclosure provide a semiconductor device, a fabrication method thereof, and a memory system. The semiconductor device includes: a memory array in a first region of the semiconductor device; first semiconductor portions located in a second region of the semiconductor device and spaced apart from each other along a first direction; a conductive structure; and an isolation structure. The second region is different from the first region; the conductive structure is on a first side of the first semiconductor portions; and the isolation structure includes a first isolation portion in the second region, where the first isolation portion extends along the first direction or a second direction, the first isolation portion extends through at least one first semiconductor portion, and the second direction intersects with the first direction.

Abstract: A memory device comprises a first array of first memory cells, first bit lines coupled to the first memory cells and extending along a bit line direction, a second array of second memory cells located adjacent to the first array of memory cells in the bit line direction, second bit lines coupled to the second memory cells and extending along the bit line direction, and an isolation structure located between the first array of first memory cells and the second array of second memory cells in the bit line direction. The isolation structure extends along the bit line direction and in contact with at least part of the first bit lines and the second bit lines.

Abstract: Three-dimensional NAND memory device and method that eliminate leakage currents and short circuits are provided. The method includes: forming a gate line slit through a plurality of alternating layers of an oxide layer and a conductive material layer, where the conductive material layer is further formed on a sidewall and a bottom of the gate line slit; performing an ion implantation process to dope at least a portion of the conductive material layer that is on the bottom and/or a portion of the sidewall of the gate line slit; and performing an etch process in the gate line slit to remove the conductive material layer that is weakened by the ion implantation process.

Abstract: A method of forming a three-dimensional (3D) NAND memory device includes: forming a gate line slit through a plurality of alternating layers of an oxide layer and a conductive material layer, where the conductive material layer is further formed on a sidewall and a bottom of the gate line slit; performing an ion implantation process to dope at least a portion of the conductive material layer that is on the bottom and/or a portion of the sidewall of the gate line slit; and performing an etch process in the gate line slit to remove the conductive material layer that is weakened by the ion implantation process.

Abstract: The present invention discloses a method for refining large-particle-size pure copper or copper alloy particles by high-energy ball milling, the method comprising the following steps: (1) using large-particle-size pure copper or copper alloy coarse particles as a raw material and cyclohexane or water as a process control agent, and crushing and refining the particles by high-energy ball milling to obtain small-particle-size copper or copper alloy powder; and (2) decreasing an oxygen content in the powder obtained in step (1) in a reducing atmosphere to obtain pure copper or copper alloy powder. In the present invention, by improving the overall process flow of the preparation method and the parameter conditions of each process step, the method greatly decreases energy consumption compared with existing copper powder preparation techniques. In addition, the method features a simple process and low production costs.