Patents by Inventor Fazil Ahmad
Fazil Ahmad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11909356Abstract: An integrated circuit transceiver device includes a plurality of functional circuits, and clock circuitry for distributing synchronous, in-phase, phase-locked clock signals to all transceiver circuits. The clock circuitry includes a frequency-controllable distributed oscillator including at least one coupled pair of transmission line oscillators having a respective oscillator core, and at least one respective transmission line segment. At least one impedance element couples the at least one respective transmission line segment of a first transmission line oscillator to the at least one respective transmission line segment of a second transmission line oscillator. Impedance of the impedance element is different from impedance of each respective transmission line segment to cause reflection at the at least one impedance element.Type: GrantFiled: June 17, 2022Date of Patent: February 20, 2024Assignee: Marvell Asia Pte LtdInventors: Morteza Azarmnia, Tomas Dusatko, Fazil Ahmad, Marco Garampazzi
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Publication number: 20230210931Abstract: A pharmaceutical composition comprising a tannin selected from 2-O-digalloyl-1,3,4,6-tetra-O-galloyl-?-D-glucose, 3-O-digalloyl-1,2,4,6-tetra-O-galloyl-?-D-glucose, 6-O-digalloyl-1,2,3,4-tetra-O-galloyl-?-D-glucose, 2,6-bis-O-digalloyl-1,3-di-O-galloyl-?-D-glucose, and 6-O-trigalloyl-1,2,3-tri-O-galloyl-?-D-glucose. The tannin may be derived from Quercus infectoria. The pharmaceutical composition is used in a method of treating cancer, particularly oral cancer.Type: ApplicationFiled: January 5, 2022Publication date: July 6, 2023Applicant: Imam Abdulrahman Bin Faisal UniversityInventors: Fazil AHMAD, Krishna Mohan SURAPANENI, Abeer Mohammed AL-SUBAIE, Balu KAMARAJ
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Publication number: 20220407458Abstract: An integrated circuit transceiver device includes a plurality of functional circuits, and clock circuitry for distributing synchronous, in-phase, phase-locked clock signals to all transceiver circuits. The clock circuitry includes a frequency-controllable distributed oscillator including at least one coupled pair of transmission line oscillators having a respective oscillator core, and at least one respective transmission line segment. At least one impedance element couples the at least one respective transmission line segment of a first transmission line oscillator to the at least one respective transmission line segment of a second transmission line oscillator. Impedance of the impedance element is different from impedance of each respective transmission line segment to cause reflection at the at least one impedance element.Type: ApplicationFiled: June 17, 2022Publication date: December 22, 2022Inventors: Morteza Azarmnia, Tomas Dusatko, Fazil Ahmad, Marco Garampazzi
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Patent number: 9859903Abstract: Method and apparatus for fast phase locked loop (PLL) settling with reduced frequency overshoot are provided. During acquisition, a first phase offset signal configured to drive a phase error signal to zero is provided at a first circuit of the PLL. The first circuit may be a time-to-digital converter (TDC) of the PLL. A second phase offset signal configured to offset the first phase offset signal is provided at a second circuit of the PLL. The second circuit of the PLL may be a loop filter at the PLL.Type: GrantFiled: January 29, 2016Date of Patent: January 2, 2018Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Greg Alyn Unruh, Pin-En Su, Fazil Ahmad
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Publication number: 20170201260Abstract: Method and apparatus for fast phase locked loop (PLL) settling with reduced frequency overshoot are provided. During acquisition, a first phase offset signal configured to drive a phase error signal to zero is provided at a first circuit of the PLL. The first circuit may be a time-to-digital converter (TDC) of the PLL. A second phase offset signal configured to offset the first phase offset signal is provided at a second circuit of the PLL. The second circuit of the PLL may be a loop filter at the PLL.Type: ApplicationFiled: January 29, 2016Publication date: July 13, 2017Inventors: Greg Alyn UNRUH, Pin-En Su, Fazil Ahmad
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Patent number: 9553714Abstract: The problem with duty-cycle correction circuits used by conventional frequency doublers is that they typically analog solutions, such as variable delay lines with long chains of inverters or buffers, that directly adjust the reference signal used by a phase-locked loop (PLL). These solutions can considerably increase the noise (e.g., thermal noise and supply noise) of the reference signal, as well as the overall power consumption and cost of the PLL. Rather than directly correct the duty-cycle of the reference signal, the present disclosure is directed to an apparatus and method for measuring the period error between adjacent cycles of a frequency doubled reference signal in terms of cycles of the output signal generated by the PLL (or some other higher frequency signal) and adjusting the division factor of the PLL frequency divider to compensate for the measured period error.Type: GrantFiled: September 30, 2015Date of Patent: January 24, 2017Assignee: Broadcom CorporationInventors: Fazil Ahmad, Pin-En Su, William Huff, Greg Unruh
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Publication number: 20160380752Abstract: The problem with duty-cycle correction circuits used by conventional frequency doubters is that they are typically analog solutions, such as variable delay lines with long chains of inverters or buffers, that directly adjust the reference signal used by a phase-locked loop (PLL). These solutions can considerably increase the noise (e.g., thermal noise and supply noise) of the reference signal, as well as the overall power consumption and cost of the PLL. Rather than directly correct the duty-cycle of the reference signal, the present disclosure is directed to an apparatus and method for measuring the period error between adjacent cycles of a frequency doubled reference signal in terms of cycles of the output signal generated by the PLL (or some other higher frequency signal) and adjusting the division factor of the PLL frequency divider to compensate for the measured period error.Type: ApplicationFiled: September 30, 2015Publication date: December 29, 2016Applicant: Broadcom CorporationInventors: Fazil AHMAD, Pin-En SU, William HUFF, Greg UNRUH
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Patent number: 9385673Abstract: Aspects of this disclosure relate to compensating for a relatively large offset in a signal generated by a sensor, such as a pressure sensor and/or a resistive bridge based sensor. Such offset compensation can include applying an offset correction signal generated by a configurable voltage reference, such as a voltage mode digital-to-analog converter (DAC), to an input of an amplifier included in an instrumentation amplifier to compensate for the offset of the signal generated by the sensor.Type: GrantFiled: July 1, 2014Date of Patent: July 5, 2016Assignee: Analog Devices GlobalInventors: Fazil Ahmad, Gavin P. Cosgrave
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Publication number: 20150236648Abstract: Aspects of this disclosure relate to compensating for a relatively large offset in a signal generated by a sensor, such as a pressure sensor and/or a resistive bridge based sensor. Such offset compensation can include applying an offset correction signal generated by a configurable voltage reference, such as a voltage mode digital-to-analog converter (DAC), to an input of an amplifier included in an instrumentation amplifier to compensate for the offset of the signal generated by the sensor.Type: ApplicationFiled: July 1, 2014Publication date: August 20, 2015Inventors: Fazil Ahmad, Gavin P. Cosgrave
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Patent number: 8786363Abstract: Apparatus and methods for electronic amplification are provided. In one embodiment, a method of electronic amplification includes amplifying a differential input voltage signal to generate a feed-forward signal, chopping the feed-forward signal at a chopping frequency to generate a chopped feed-forward signal, notch filtering the chopped feed-forward signal at the chopping frequency to generate a notched signal, generating an input offset correction signal based at least partly on the notched signal, and amplifying the differential input voltage signal using a signal amplification block to generate an output signal. Amplifying the differential input voltage signal using the signal amplification block includes chopping the input signal at the chopping frequency to generate a chopped input signal and combining the chopped input signal and the offset correction signal to reduce input offset error of the signal amplification block.Type: GrantFiled: June 13, 2012Date of Patent: July 22, 2014Assignee: Analog Devices, Inc.Inventor: Fazil Ahmad
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Patent number: 8638166Abstract: Apparatus and methods for notch filtering are provided. In certain implementations, an amplifier includes amplification stages for providing signal amplification, chopper circuitry for generating a chopped signal by chopping an amplified signal associated with the amplification stages at a chopping frequency, and a time-interleaved finite impulse response (FIR) notch filter for notching frequency components of the chopped signal near the chopping frequency. The time-interleaved FIR notch filter includes a plurality of FIR filters configured to sample the chopped signal at a sampling rate of about twice the chopping frequency. The FIR filters are interleaved in time to reduce sampling error. Additionally, the time-interleaved FIR notch filter includes an infinite impulse response (IIR) filter configured to average samples taken by respective ones of the FIR filters and to integrate the averaged samples to generate the time-interleaved FIR notch filter's output signal.Type: GrantFiled: June 13, 2012Date of Patent: January 28, 2014Assignee: Analog Devices, Inc.Inventor: Fazil Ahmad
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Publication number: 20130335141Abstract: Apparatus and methods for electronic amplification are provided. In one embodiment, a method of electronic amplification includes amplifying a differential input voltage signal to generate a feed-forward signal, chopping the feed-forward signal at a chopping frequency to generate a chopped feed-forward signal, notch filtering the chopped feed-forward signal at the chopping frequency to generate a notched signal, generating an input offset correction signal based at least partly on the notched signal, and amplifying the differential input voltage signal using a signal amplification block to generate an output signal. Amplifying the differential input voltage signal using the signal amplification block includes chopping the input signal at the chopping frequency to generate a chopped input signal and combining the chopped input signal and the offset correction signal to reduce input offset error of the signal amplification block.Type: ApplicationFiled: June 13, 2012Publication date: December 19, 2013Applicant: Analog Devices, Inc.Inventor: Fazil Ahmad
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Publication number: 20130335144Abstract: Apparatus and methods for notch filtering are provided. In certain implementations, an amplifier includes amplification stages for providing signal amplification, chopper circuitry for generating a chopped signal by chopping an amplified signal associated with the amplification stages at a chopping frequency, and a time-interleaved finite impulse response (FIR) notch filter for notching frequency components of the chopped signal near the chopping frequency. The time-interleaved FIR notch filter includes a plurality of FIR filters configured to sample the chopped signal at a sampling rate of about twice the chopping frequency. The FIR filters are interleaved in time to reduce sampling error. Additionally, the time-interleaved FIR notch filter includes an infinite impulse response (IIR) filter configured to average samples taken by respective ones of the FIR filters and to integrate the averaged samples to generate the time-interleaved FIR notch filter's output signal.Type: ApplicationFiled: June 13, 2012Publication date: December 19, 2013Applicant: Analog Devices, Inc.Inventor: Fazil Ahmad
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Patent number: 7782234Abstract: The method and system for converting an analog value into a digital equivalent using a plurality of conversion engines are disclosed. In one embodiment the plurality of conversion engines comprise N DACs associated with M comparators, wherein M is substantially greater than N, wherein M and N are integers, wherein each of the N CAP DACs has an associated P CAP DAC and an N CAP DAC, a method includes generating voltage differences between P CAP DACs and N CAP DACs such that they produce M threshold voltages. The plurality of conversion engines operate in a first phase of the conversion by inputting the produced M threshold voltages to associated inputs of M comparators so that more than one bit can be determined from a sampled signal during each successive approximation trial.Type: GrantFiled: May 31, 2007Date of Patent: August 24, 2010Assignee: Analog Devices, Inc.Inventor: Fazil Ahmad
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Publication number: 20090109079Abstract: The method and system for converting an analog value into a digital equivalent using a plurality of conversion engines are disclosed. In one embodiment the plurality of conversion engines comprise N DACs associated with M comparators, wherein M is substantially greater than N, wherein M and N are integers, wherein each of the N CAP DACs has an associated P CAP DAC and an N CAP DAC, a method includes generating voltage differences between P CAP DACs and N CAP DACs such that they produce M threshold voltages. The plurality of conversion engines operate in a first phase of the conversion by inputting the produced M threshold voltages to associated inputs of M comparators so that more than one bit can be determined from a sampled signal during each successive approximation trial.Type: ApplicationFiled: May 31, 2007Publication date: April 30, 2009Inventor: FAZIL AHMAD