Abstract: A switching fabric for transmitting digital data from a plurality of sources to a plurality of destinations is described. The switching fabric includes a plurality of input ports, a plurality of output ports and a plurality of switching sections. Each of the input ports receives data frames and partitions the received data payload of at least some of the frames into a plurality of associated data cells. Each of the output ports are coupled to at least one destination associated with the headers of the data frames. Each of the switching sections may be coupled to each of the input ports and each of the output ports for transmitting each of selected ones of the data cells from the at least one input port to one or more of the coupled output ports.

Abstract: A method and apparatus for coupling a signal from one node to another node prepares a signal for transmission, performs error checking on such signal while simultaneously transferring such signal within a transmitting node, transmits the signal from the transmitting node, receives and formats the signal at a receiving node, including an identifying portion and a data portion, and directly stores the data portion in memory that is directly accessible by a user process executing in the receiving node while simultaneously performing error checking.

Abstract: A circuit which operates on input signals representing multiformatted sequences of idle characters, voice characters, and data characters comprises: a first state machine consisting essentially of a logic array, a register, and a counter. One section of the register is coupled to receive the input signals and another section of the register together with the counter is coupled to receive respective signals from the logic array. The logic array has input terminals coupled to receive signals from the register and the counter, and in response, generate control signals indicating in which format and which location therein each character is being received. Second, third, and fourth state machines are coupled to receive respective subsets of the control signals from the first state machine.

Abstract: A method of transmitting isochronous and nonisochronous data in a computer network in which multiple stations have respective input and output ports that are serially coupled together to form a loop includes the steps of: transmitting nonisochronous data from one station of the network and passing it through the remaining stations; periodically inserting into the nonisochronous data a lead control character followed by a trail control character and circulating the control characters twice around the network; increasing, in any station of the network that has isochronous data to send, the distance between the lead and trail control characters and sending isochronous data immediately before the trail control character as it passes through the station; subsequently decreasing the distance between the lead and trail control characters in each station of the network that performs the sending step by removing, from immediately behind the first lead control character to enter the station after the sending step begin

Abstract: A dynamic re-programmable logic array is disclosed which has an AND array disposed for receiving n input signals, an OR array providing k output signals on k output lines and m term lines and m bit lines coupling the AND and OR arrays, wherein the array comprises new and improved random access AND and OR arrays incorporating programmable charge storage elements. Refresh logic is also provided for periodically restoring the charge programmed on the charge storage elements.

Abstract: In the disclosed error-correcting memory, data bits are stored in a plurality of memory arrays. Each of said arrays have their memory cells arranged in rows and columns, and a word of said data bits is read by simultaneously selecting one cell at any one row-column pair in every array of said plurality. Every row of each array of said plurality includes a means for storing at least one code bit computed from the data bits in the corresponding row. A plurality of checking means respectively coupled to said plurality of arrays for receiving and checking all of the data bits and code bits in the row in its corresponding array from which said one cell is selected to form said word. And an additional memory array means contains memory cells arranged in rows and columns for storing a parity bit at each row-column pair computed from the word of data bits in said plurality of arrays at the corresponding row-column pair.