Abstract: Apparatuses and methods related to error correction via artificial intelligence (AI) are described. An augmented reality (AR) display can be coupled to a memory device. AI circuitry coupled to the memory device can receive an error correction model. Prior to receipt of the error correction model by the AI circuitry, the error correction model can be trained, externally to the memory device and AI circuitry, to correct random errors introduced to execution of the AR AI workload in hazardous conditions. The AI circuitry can execute the model to perform error correction in association with execution of the AR AI workload.

Abstract: The present disclosure includes apparatuses, methods, and systems for classifying an area as hazardous or non-hazardous based on an operation of a semiconductor device. In an example, an apparatus can include a memory configured to store a global operation model and a processor coupled to the memory wherein the processor is configured to receive test data and operating data from a semiconductor device based on operation of the semiconductor device in an area, run the global operation model on the test data and the operating data from the semiconductor device to generate output data, and classify the area as hazardous or non-hazardous based on the output data.

Abstract: Techniques of nonlinear quantization of an artificial neural network model having first weights. For example, a predetermined number of unique, second weights having a nonlinear distribution in a weight space of the first weights can be identified to generate a quantized model based on replacing, in the artificial neural network model, the first weights with closest ones from the second weights. A linear mapping between the second weights and values of conductance of memristors of an accelerator configured to perform operations of multiplication and accumulation can be used to determine the same predetermined number of programming voltages. Conductance of the memristors can be programmed using the programming voltages in preparation of the accelerator to perform an operation of multiplication and accumulation in the quantized model. The nonlinear distribution and the linear mapping can be adjusted to increase or optimize the accuracy of the quantized model.

Abstract: Customization of deep learning models for accelerators of multiplication and accumulation operations. Based on a type of an accelerator to be used to implement the computation of an artificial neural network, a weight matrix of an artificial neural network can be adjusted, during training or via re-training, based on energy consumption characteristics of the type of accelerators. Patterns of weights that can consume more energy in computations implemented via the accelerator can be suppressed via penalizing by a loss function during training, or via pruning and re-training. The adjusted weight matrix can be configured in a computing device having an accelerator of the type. When the computing device performs computations of the artificial neural network using the weight matrix, the accelerator can be used to accelerate multiplication and accumulation operations involving the weight matrix.

Abstract: Systems, methods, and apparatuses related to channel management are described herein. An optical communication system can comprise an optical source configured to send optical signals, a meta-waveguide having a limited quantity of channels, the meta waveguide coupled to the optical source and configured to transport the optical signals, and a controller coupled to the optical source and the meta-waveguide, the controller configured to determine a type of data to be sent via the meta-waveguide, cause optical signals indicative of the data to be sent through at least one of the channels, and cause a gap comprising at least one unutilized channel to be reserved between the at least one channel and another utilized channel depending on the type of data.

Abstract: Apparatuses, non-transitory machine-readable media, and methods associated with passive photonic physically unclonable functionality for securing an automotive powertrain control area network are described herein. One apparatus includes a first network node communicatively connected via photonic interconnections to a second network node, the first network node has a passive photonic encryption unit for encrypting data packets by utilizing a microring resonator (MR) having at least one fabrication process variation (FPV) that is unique from the MRs of the other nodes, a decryption unit having a look up table (LUT) including at least one node identifier and containing information about at least one FPV of one of the network nodes to decrypt data packets, and a processing unit that processes the contents of the decrypted data packets.

Abstract: Systems, methods, and apparatuses related to a network for behavior modeling are described. A network can include surveillance devices that are each configured to collect pedestrian behavior data corresponding to a geographic region and output local pedestrian behavior model updates to a municipal communication node for the geographic region. The municipal communication node is configured to receive the local pedestrian behavior model updates and output the local pedestrian behavior model updates to a global pedestrian behavior model to aggregate the local pedestrian behavior model updates. A processing device is coupled to the municipal communication node and is configured to output the global pedestrian behavior model to the municipal communication node.

Abstract: Apparatuses and methods related to defining a parking area are described. In an example, an apparatus can include a memory and a processor coupled to the memory, wherein the processor is configured to receive vehicle data, receive sensor data of a parking lot, and define a parking area within the parking lot for a vehicle to park based on the received vehicle data and the received sensor data.

Abstract: A photonic probing system, including a communication bus for communicating a main photonic waveguide signal therethrough, a splitter that splits off a portion of the main photonic waveguide signal to create an off-shoot portion photonic signal, a photodetector that converts the off-shoot portion photonic signal to a converted electrical current, a current threshold detector that compares the converted electrical current to a threshold value to determine if the converted electrical current exceeds the threshold value, if the converted electrical current does not exceed the threshold value, then the current threshold detector generates a laser generating signal directed toward a VCSEL, and wherein the laser generating signal drives the VCSEL to generate a laser signal directed toward a central control system.

Abstract: Modifying values stored in memory cells based on process variation can include receiving process variation information for a first plurality of memory cells of a memory array. A plurality of values to be stored in the memory cells can be modified based on the process variation information. The plurality of instructions to store the plurality of values in a second plurality of memory cells can be compiled. The plurality of modified values can also be stored in a second plurality of memory cells at run time.

Abstract: Updating a distribution of voltage-conductance points for artificial neural networks can include receiving, at an accelerator, such as a MAC unit, information corresponding to a memory array of the MAC unit. A plurality of parameters of the ANN can be received. The distribution of voltage-conductance points can be identified utilizing the plurality of parameters and based on the information corresponding to the memory array. The distribution of voltage-conductance points correspond to discernable conductance levels and a subset of the plurality of parameters. The ANN can be stored in the MAC unit based on the discernable conductance levels.

Abstract: A computing system having a photonic interconnect system configured between a plurality of memory sub-systems and a plurality of processing elements. The photonic interconnect system includes a plurality of first optical interface modules connected to the plurality of processing elements respectively; a plurality of second optical interface modules connected to the plurality of memory sub-systems respectively; and a photonic switch configured between the plurality of first optical interface modules and the plurality of second optical interface modules. The photonic interconnect system can dynamically allocate virtual communication channels, implemented via optical signals of different wavelengths in the photonic interconnect system, between the plurality of processing elements and the plurality of memory sub-systems.

Abstract: Techniques to access memory in a systolic pattern. For example, a processor sub-system is connected between a first memory sub-system and a second memory sub-system. In response to a first clock signal, a communication direction of a first connection between the processor sub-system and the first memory sub-system is configured to receive first data in the processor sub-system from the first memory sub-system; and a communication direction of a second connection between the processor sub-system and the second memory sub-system is configured to transmit second data from the processor sub-system to the second memory sub-system. In response to a second clock signal, the communication direction of the first connection and the communication direction of the second connection are reversed.

Abstract: A controller of a high bandwidth interconnect between a memory sub-system and a processor sub-system configured to regulate access to memories in the memory sub-system. Using data indicative of memory access activities in a plurality of memories during a first time period, the controller can evaluate thermal stresses in memories during a first time period, group memories into memory batches, and schedule and imposing, idle times for the batches in a second time period following the first time period. After receiving requests to access the plurality of memories during the second time period, the controller can throttle communications of the requests to memory controllers and/or to the memory sub-system to enforce the idle times pre-scheduled for the memory batches in the second time period.

Abstract: A computing system having a photonic interconnect configured between a memory sub-system having a plurality of memory islands and a host system running one or more applications using memory provide by an active subset of the memory islands. The memory sub-system includes a direct memory access controller operable to transfer data between the other memory islands of the memory sub-system, while the host system runs on the active subset. The photonic interconnect can be configured to distribute its communication bandwidth to the active subset without being effected by the direct memory access operations performed on memory islands outside of the active subset.

Abstract: The present disclosure includes apparatuses, methods, and systems for displaying output data from a driver attention model on a display. In an example, an apparatus can include a sensor, an augmented reality (AR) windshield, a memory, and a processor coupled to the memory, the sensor, and the AR windshield, wherein the processor is configured to receive an initial driver attention model, train the initial driver attention model to create a trained driver attention model, transmit the trained driver attention model, receive a global driver attention model based in part on the trained driver attention model, receive sensor data based on operation of the apparatus, run the global driver attention model on the sensor data to generate output data, and cause the output data to be displayed on the AR windshield.

Abstract: A computing system having a plurality of memory sub-systems and a central host. Each of the memory sub-systems has a first optical interface module. The central host has second optical interface module. The central host and the plurality of memory sub-systems are connected through a plurality of optical fibers in a ring topology network of connections. The central host can partition computations of an application into multiple parts executable in a pipeline to perform the computations of the application. The central host can write data specifying computations of the parts into the memory sub-systems and instruct the memory sub-systems to perform pipelined processing of the parts via communications over the ring topology network of connections.

Abstract: Training an artificial neural network (ANN) can include receiving device design parameters corresponding to a device and operation parameters corresponding to the device. Device throughput characteristics can also be received from a physics solver. Device throughput predictions can be generated utilizing the device design parameters, the operation parameters, and an artificial neural network. A loss gradient can be generated utilizing the device throughput characteristics and the device throughput predictions. The ANN can be trained, utilizing the loss gradient, to generate different device throughput predictions.

Abstract: Apparatuses and methods related to error correction via artificial intelligence (AI) are described. An augmented reality (AR) display can be coupled to a memory device. AI circuitry coupled to the memory device can receive an error correction model. Prior to receipt of the error correction model by the AI circuitry, the error correction model can be trained, externally to the memory device and AI circuitry, to correct random errors introduced to execution of the AR AI workload in hazardous conditions. The AI circuitry can execute the model to perform error correction in association with execution of the AR AI workload.

Abstract: An apparatus having a plurality of accelerators of different types for operations of multiplication and accumulation. In response to a request to perform a task of multiplication and accumulation on input data, the apparatus can analyze the input data to determine characteristics of the input data. The characteristics are indicative of energy efficiency levels of the accelerators in performing the task. The apparatus can assign the task to one of the accelerators based on the characteristics for improved energy efficiency, in addition to balancing workloads for the accelerators. For example, the different types of accelerators can include accelerators configured to perform multiplication and accumulation using microring resonators, synapse memory cells, logical multiply-accumulate units, memristors, etc.